# Core memory The store half of the Setun design. Scope is deliberately narrow: the ferrite core array, its addressing, the trit encoding, and how it would be built now. The logic element is a different physical object (wound cores, many turns, used as threshold amplifiers) and is covered in `logic-element.md`. ## What Setun actually had Known from Brusentsov's own descriptions and the 2006 SORUCOM paper: - Operating store: 162 cells of 9 trits. Organised as 3 pages of 54 cells, exchanged page-wise with the drum. It functioned as a fast level, effectively a cache. - Backing store: magnetic drum, 1944 or 3888 cells of 9 trits, i.e. 36 or 72 pages. Average page transfer 7500 us. - Word formats: instruction 9 trits, accumulator and return registers 18 trits, index register and counter 5 trits, sign 1 trit. Converted: the core array is 1458 trits, about 2.3 kbit. The drum is 17 496 trits, about 28 kbit, or double that in the larger configuration. The drum is not core memory and is a separate problem. It is mentioned here only because the page structure explains why the core array is as small as it is: the machine was designed around a two-level store. ## Two technologies, often conflated This matters for manufacturing and it is where most summaries go wrong. - Logic element: wound. A core with a large number of turns, operating as a current-pulse magnetic amplifier. Fifty-odd turns per core, done on a toroid winder or by hand with a needle. - Memory element: threaded. Each core sits in a plane and has one or a few wires passed through it once. Selection is by coincidence of half currents on an X and a Y line, so no per-core access wiring exists. Historically the first was automated early and the second resisted automation for two decades. Core *manufacture* (pressing and firing the ferrite) was fully industrial, IBM reached 20 billion cores a year at $0.0003 each. Core *plane assembly* stayed hand work, rows of operators threading wires through cores under magnification. Do not import the winding argument into the plane: a winder does not help here, and a threading gantry is a much harder machine. For the sizes involved in this project the plane is a bench job anyway. A few thousand cores is weeks of hand work, not an industrial line. ## Storing a trit Chapter X section 1 settles this, and it corrects the secondary sources. A trit does not use a two-bit code with an unused fourth state. It uses two cores in a genuinely three-valued scheme: - +1 and -1 are the two saturated states, with the pair magnetised in opposite senses relative to the current in the number circuit, one direction for +1 and the reverse for -1. - 0 is not a saturated state. Each core is left with its inner and outer layers magnetised in opposite directions, so the net flux in each is close to zero. The zero lives in a partial-switching state of the core wall, not in a combination of two binary values. The pair is wired so that the two induced EMFs are differenced onto the sense line. That is what makes the read work: +1 flips only core A, -1 flips only core B, 0 flips only the inner layers of both and the differential EMF cancels to nearly nothing. Three distinguishable outcomes from two cores, no unused state. Sizing is unchanged: 1458 trits, two cores each, 2916 cores. The information density is worse than binary core memory, 1.585 bits per two cores, which is the price of storing ternary in the medium instead of coding it in. ## Reading and writing Standard core behaviour, listed because the century-durability argument depends on it: - Read is destructive. The core is driven to a known state and the sense line detects whether it flipped. Every read must be followed by a rewrite. - Selection is two-stage and the split matters for wiring. The address is 5 trits. Trits 1 and 2 drive one decoder, trits 3 and 4 drive another, giving a 9 by 9 matrix of 81 coordinate transformers per half-cube, with trit 5 choosing the half. Two half currents meet at one transformer and only that one switches. Coincidence therefore applies at word level, in the transformer matrix, not at the cores. - The digits are directly selected. Each coordinate transformer's secondary feeds the number circuit of one 9-trit word, which is 9 core pairs in series. Once the transformer fires, the whole word is driven at once and no core ever sees a half current. The book calls this direct selection, system A. It also explains the sense amplifier: with no half-select neighbours on the digit cores, the only noise is the bias arrangement. - Read is destructive and self-restoring in one cycle. When the half-current pulses end, a bias current flows in the reverse direction, and the write pulse arrives on the same sense/write wire, adding to the bias in one core and subtracting in the other. The sum flips one core, the difference is not enough to flip the other. For 0 no write pulse is applied and the bias alone flips only the inner layers. - Writing needs a third line, the inhibit wire, to suppress the flip in the cores that should stay at zero. - The sense line is shared across the plane, so the amplifier discriminates a full-select signal against the noise of many half-selected cores. Two consequences for a machine meant to last a century. First, destructive read means a word is torn if power fails mid-cycle, so either hold up the supply long enough to finish the rewrite or make the controller able to detect and repair a torn word at boot. Second, the sense threshold drifts with temperature and with core ageing, so margins must be measurable in situ, not just designed in on paper. Build in a mode that sweeps drive current and reports the margin, and the machine can be recalibrated by a technician in 2126 without a logic analyser. ## Why it suits a century machine - Non-volatile. No refresh, no standby power to retain, no battery. - Radiation and EMP tolerant. There is no charge to lose and no junction to latch, which is the usual failure mode of semiconductor stores in both cases. - Inspectable and repairable. A dead core or a broken wire is visible and localisable. A dead DRAM cell is not, and a dead flash block is not. - Nothing in the storage element wears out. The wear items are the diodes, the drive electronics and the wire insulation, all replaceable. Counterweights, so this does not read as advocacy: the drive currents need a real supply, the sense amplifiers are the precision part and are the actual engineering difficulty, and the array is physically large per bit compared with anything modern. The size is the price of the durability. ## What I would build Ordered by what removes risk soonest, not by elegance. 1. Word-serial selection on the digit side, coincidence only in the word matrix. This is exactly what Setun already did, and it is the right answer for a rebuild: the matrix keeps the decoder small, while driving a whole word at once removes half-select noise from the most delicate part, the sense amplifier. 2. Two cores per trit, 2916 cores for the Setun-sized array. Thread by hand with a jig, in batches, and document the jig, because the jig is the actual intellectual property here. 3. Bin the cores before assembly. Measure the switching threshold of every core and group them into matched sets per plane. This is the step that made Setun's cells expensive in 1958: selection, not assembly. The tester is the machine worth building first. 4. Record a per-core map in the repository: position, measured threshold, date, operator. A technician replacing a core in fifty years needs to know what it was supposed to be. 5. Automate the tester and the binning. Automate threading only if the array grows past what a person will do, which at these sizes it probably will not. ## Open questions Settled by the book: - Trit encoding: two cores, three genuine states, zero as a zero-flux partial-switching state. Not a two-bit code. - Addressing: 5-trit address, 9 by 9 coordinate-transformer matrix per half-cube, direct selection of the 9 digit pairs, 81 words per half. Still open: - Drum construction, and whether a drum is reproducible at all now. Chapter XI has the block, the control unit, write pulse shaping and read amplification, so the answer exists in the scan and is simply unread. - Sense amplifier design that is century-stable without custom silicon. Chapter X section 3 has the original, built from valves and then transistors. - Whether the zero state holds for decades. It is a partial-switching state, so it is the least obviously stable thing in the design and the first thing worth measuring on real cores. - The logic element is the same physics at a different scale, so chapter VII is the companion read: fast magnetic amplifier on current-pulse supply, then the basic logic cells. ## Sources - Scan: github.com/askfind/Ternary-Computer-SETUN-Documentation, file Setun-1958/Small_digital_ternary_computer_Setun_1965.pdf, 149 pages, image only, no text layer. Same repository holds the 1965 technical manual (djvu), the 1972 threshold logic paper, the 1964 magnetic elements volume, and whole runs of Vychislitelnaya Tekhnika i Voprosy Kibernetiki. - Local: ~/s/setun-ref/, with tessdata/rus.traineddata. Renders at 400 dpi greyscale OCR reliably with tesseract. - Chapter map: VII logic elements, X core store, XI drum, XIV power and the current-pulse generator. - All quotations above are OCR of a 1965 scan. The mechanism is unambiguous; individual numerals should be checked against the page images.