Acquire an FPGA unit with sufficient logic cell density to map lattice nodes 1:1 onto processing elements. The BFS demand wavefront, gradient descent, and bonding all become physical signal propagation — O(diameter) clock cycles instead of O(V+E) sequential steps. The graph topology becomes the circuit topology: no pointers, no queues, no cache misses. Each node computes simultaneously.
Target: a device with at least 4096 logic cells (4 blocks worth of nodes) with local SRAM per cell for node state (occupant, constraints, demand distance). Inter-cell routing maps to the lattice neighbor topology. Xilinx Artix-7 or Lattice ECP5 class devices are the minimum viable density. Larger runs (full lattice, 10K+ nodes) need Kintex/Ultrascale class or equivalent.