cpuid_arm64.s raw

   1  // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
   2  
   3  //+build arm64,!gccgo,!noasm,!appengine
   4  
   5  // See https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt
   6  
   7  // func getMidr
   8  TEXT ·getMidr(SB), 7, $0
   9  	WORD $0xd5380000    // mrs x0, midr_el1         /* Main ID Register */
  10  	MOVD R0, midr+0(FP)
  11  	RET
  12  
  13  // func getProcFeatures
  14  TEXT ·getProcFeatures(SB), 7, $0
  15  	WORD $0xd5380400            // mrs x0, id_aa64pfr0_el1  /* Processor Feature Register 0 */
  16  	MOVD R0, procFeatures+0(FP)
  17  	RET
  18  
  19  // func getInstAttributes
  20  TEXT ·getInstAttributes(SB), 7, $0
  21  	WORD $0xd5380600            // mrs x0, id_aa64isar0_el1 /* Instruction Set Attribute Register 0 */
  22  	WORD $0xd5380621            // mrs x1, id_aa64isar1_el1 /* Instruction Set Attribute Register 1 */
  23  	MOVD R0, instAttrReg0+0(FP)
  24  	MOVD R1, instAttrReg1+8(FP)
  25  	RET
  26  
  27  TEXT ·getVectorLength(SB), 7, $0
  28  	WORD $0xd2800002  // mov   x2, #0
  29  	WORD $0x04225022  // addvl x2, x2, #1
  30  	WORD $0xd37df042  // lsl   x2, x2, #3
  31  	WORD $0xd2800003  // mov   x3, #0
  32  	WORD $0x04635023  // addpl x3, x3, #1
  33  	WORD $0xd37df063  // lsl   x3, x3, #3
  34  	MOVD R2, vl+0(FP)
  35  	MOVD R3, pl+8(FP)
  36  	RET
  37