asm9.go raw
1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova.
2 //
3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
5 // Portions Copyright © 1997-1999 Vita Nuova Limited
6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
7 // Portions Copyright © 2004,2006 Bruce Ellis
8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
10 // Portions Copyright © 2009 The Go Authors. All rights reserved.
11 //
12 // Permission is hereby granted, free of charge, to any person obtaining a copy
13 // of this software and associated documentation files (the "Software"), to deal
14 // in the Software without restriction, including without limitation the rights
15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 // copies of the Software, and to permit persons to whom the Software is
17 // furnished to do so, subject to the following conditions:
18 //
19 // The above copyright notice and this permission notice shall be included in
20 // all copies or substantial portions of the Software.
21 //
22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 // THE SOFTWARE.
29
30 package ppc64
31
32 import (
33 "github.com/twitchyliquid64/golang-asm/obj"
34 "github.com/twitchyliquid64/golang-asm/objabi"
35 "encoding/binary"
36 "fmt"
37 "log"
38 "math"
39 "sort"
40 )
41
42 // ctxt9 holds state while assembling a single function.
43 // Each function gets a fresh ctxt9.
44 // This allows for multiple functions to be safely concurrently assembled.
45 type ctxt9 struct {
46 ctxt *obj.Link
47 newprog obj.ProgAlloc
48 cursym *obj.LSym
49 autosize int32
50 instoffset int64
51 pc int64
52 }
53
54 // Instruction layout.
55
56 const (
57 funcAlign = 16
58 funcAlignMask = funcAlign - 1
59 )
60
61 const (
62 r0iszero = 1
63 )
64
65 type Optab struct {
66 as obj.As // Opcode
67 a1 uint8
68 a2 uint8
69 a3 uint8
70 a4 uint8
71 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r
72 size int8
73 param int16
74 }
75
76 // This optab contains a list of opcodes with the operand
77 // combinations that are implemented. Not all opcodes are in this
78 // table, but are added later in buildop by calling opset for those
79 // opcodes which allow the same operand combinations as an opcode
80 // already in the table.
81 //
82 // The type field in the Optabl identifies the case in asmout where
83 // the instruction word is assembled.
84 var optab = []Optab{
85 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0},
86 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0},
87 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0},
88 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0},
89 /* move register */
90 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0},
91 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0},
92 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0},
93 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0},
94 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0},
95 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
96 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
97 {AADD, C_SCON, C_REG, C_NONE, C_REG, 4, 4, 0},
98 {AADD, C_SCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
99 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
100 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
101 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0},
102 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0},
103 {AADD, C_ANDCON, C_REG, C_NONE, C_REG, 22, 8, 0},
104 {AADD, C_ANDCON, C_NONE, C_NONE, C_REG, 22, 8, 0},
105 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
106 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
107 {AADDIS, C_ADDCON, C_REG, C_NONE, C_REG, 20, 4, 0},
108 {AADDIS, C_ADDCON, C_NONE, C_NONE, C_REG, 20, 4, 0},
109 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
110 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
111 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
112 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
113 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
114 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
115 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */
116 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
117 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
118 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
119 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0},
120 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0},
121 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
122 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0},
123 {AANDCC, C_ADDCON, C_NONE, C_NONE, C_REG, 23, 8, 0},
124 {AANDCC, C_ADDCON, C_REG, C_NONE, C_REG, 23, 8, 0},
125 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0},
126 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0},
127 {AANDISCC, C_ANDCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
128 {AANDISCC, C_ANDCON, C_REG, C_NONE, C_REG, 59, 4, 0},
129 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
130 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
131 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
132 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
133 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
134 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
135 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
136 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
137 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0},
138 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0},
139 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0},
140 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0},
141 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */
142 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
143 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0},
144 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0},
145 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
146 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0},
147 {AOR, C_ADDCON, C_NONE, C_NONE, C_REG, 23, 8, 0},
148 {AOR, C_ADDCON, C_REG, C_NONE, C_REG, 23, 8, 0},
149 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0},
150 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0},
151 {AORIS, C_ANDCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
152 {AORIS, C_ANDCON, C_REG, C_NONE, C_REG, 59, 4, 0},
153 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */
154 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
155 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */
156 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0},
157 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
158 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
159 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
160 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
161 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0},
162 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0},
163 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0},
164 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0},
165 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
166 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
167 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0},
168 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0},
169 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
170 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
171 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0},
172 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0},
173 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0},
174 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0},
175 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0},
176 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0},
177 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0},
178 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0},
179 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0},
180 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0},
181 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0},
182 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0},
183 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0},
184 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0},
185 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0},
186 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0},
187 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0},
188 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0},
189 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0},
190
191 /* store, short offset */
192 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
193 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
194 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
195 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
196 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
197 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
198 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
199 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
200 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
201 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
202 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
203 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
204 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
205 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
206 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
207 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
208 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
209 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
210 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
211 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
212 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
213 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
214 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
215 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
216
217 /* load, short offset */
218 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
219 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
220 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
221 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
222 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
223 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO},
224 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO},
225 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
226 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
227 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
228 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
229 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB},
230 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
231 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
232 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
233 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
234 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP},
235 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
236 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
237 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
238 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
239 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
240 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO},
241 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO},
242
243 /* store, long offset */
244 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
245 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
246 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
247 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
248 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
249 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
250 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
251 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
252 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
253 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
254 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
255 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
256 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
257 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
258 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
259 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
260 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
261 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
262 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
263 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
264
265 /* load, long offset */
266 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
267 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
268 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
269 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
270 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB},
271 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
272 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
273 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
274 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
275 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP},
276 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
277 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
278 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
279 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
280 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO},
281 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
282 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
283 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
284 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
285 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0},
286
287 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0},
288 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0},
289
290 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0},
291 {AMOVD, C_TOCADDR, C_NONE, C_NONE, C_REG, 95, 8, 0},
292
293 /* load constant */
294 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB},
295 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
296 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
297 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
298 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
299 {AMOVD, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
300 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */
301 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
302 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
303 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
304 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
305 {AMOVW, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
306 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */
307 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
308 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
309 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
310 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
311 {AMOVWZ, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
312
313 /* load unsigned/long constants (TO DO: check) */
314 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
315 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
316 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
317 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
318 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
319 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
320 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0},
321 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
322 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
323 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
324 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0},
325 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0},
326 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0},
327 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0},
328 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0},
329 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0},
330 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0},
331 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0},
332 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0},
333 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0},
334 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0},
335 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0},
336 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0},
337 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0},
338 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0},
339 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0},
340 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0},
341 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0},
342 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB},
343 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP},
344 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO},
345 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB},
346 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP},
347 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO},
348 {AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 24, 4, 0},
349 {AFMOVD, C_ADDCON, C_NONE, C_NONE, C_FREG, 24, 8, 0},
350 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0},
351 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
352 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
353 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
354 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
355 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
356 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
357 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
358 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0},
359 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0},
360 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
361 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
362 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0},
363 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0},
364 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0},
365 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0},
366 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0},
367 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0},
368 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0},
369 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0},
370 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0},
371 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0},
372 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0},
373 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0},
374 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0},
375 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0},
376 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0},
377 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0},
378 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0},
379 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0},
380 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0},
381 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0},
382 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0},
383 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0},
384 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0},
385 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0},
386 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */
387 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */
388 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */
389
390 /* Other ISA 2.05+ instructions */
391 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */
392 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */
393 {ACMPEQB, C_REG, C_REG, C_NONE, C_CREG, 92, 4, 0}, /* compare equal byte, x-form, ISA 3.0 */
394 {ACMPEQB, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0},
395 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */
396 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */
397 {ACOPY, C_REG, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* copy/paste facility, x-form */
398 {ADARN, C_SCON, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* deliver random number, x-form */
399 {ALDMX, C_SOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, /* load doubleword monitored, x-form */
400 {AMADDHD, C_REG, C_REG, C_REG, C_REG, 83, 4, 0}, /* multiply-add high/low doubleword, va-form */
401 {AADDEX, C_REG, C_REG, C_SCON, C_REG, 94, 4, 0}, /* add extended using alternate carry, z23-form */
402 {ACRAND, C_CREG, C_NONE, C_NONE, C_CREG, 2, 4, 0}, /* logical ops for condition registers xl-form */
403
404 /* Vector instructions */
405
406 /* Vector load */
407 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */
408
409 /* Vector store */
410 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */
411
412 /* Vector logical */
413 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */
414 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */
415
416 /* Vector add */
417 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */
418 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */
419 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */
420 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */
421 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */
422
423 /* Vector subtract */
424 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */
425 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */
426 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */
427 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */
428 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */
429
430 /* Vector multiply */
431 {AVMULESB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 9}, /* vector multiply, vx-form */
432 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */
433 {AVMSUMUDM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector multiply-sum, va-form */
434
435 /* Vector rotate */
436 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */
437
438 /* Vector shift */
439 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */
440 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */
441 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */
442
443 /* Vector count */
444 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */
445 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */
446
447 /* Vector compare */
448 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */
449 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */
450 {AVCMPNEZB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare not equal, vx-form */
451
452 /* Vector merge */
453 {AVMRGOW, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector merge odd word, vx-form */
454
455 /* Vector permute */
456 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */
457
458 /* Vector bit permute */
459 {AVBPERMQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector bit permute, vx-form */
460
461 /* Vector select */
462 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */
463
464 /* Vector splat */
465 {AVSPLTB, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */
466 {AVSPLTB, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0},
467 {AVSPLTISB, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */
468 {AVSPLTISB, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0},
469
470 /* Vector AES */
471 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */
472 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */
473 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */
474
475 /* Vector SHA */
476 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */
477
478 /* VSX vector load */
479 {ALXVD2X, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */
480 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 96, 4, 0}, /* vsx vector load, dq-form */
481 {ALXVL, C_REG, C_REG, C_NONE, C_VSREG, 98, 4, 0}, /* vsx vector load length */
482
483 /* VSX vector store */
484 {ASTXVD2X, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */
485 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 97, 4, 0}, /* vsx vector store, dq-form */
486 {ASTXVL, C_VSREG, C_REG, C_NONE, C_REG, 99, 4, 0}, /* vsx vector store with length x-form */
487
488 /* VSX scalar load */
489 {ALXSDX, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */
490
491 /* VSX scalar store */
492 {ASTXSDX, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */
493
494 /* VSX scalar as integer load */
495 {ALXSIWAX, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */
496
497 /* VSX scalar store as integer */
498 {ASTXSIWX, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */
499
500 /* VSX move from VSR */
501 {AMFVSRD, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */
502 {AMFVSRD, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0},
503 {AMFVSRD, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0},
504
505 /* VSX move to VSR */
506 {AMTVSRD, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */
507 {AMTVSRD, C_REG, C_REG, C_NONE, C_VSREG, 88, 4, 0},
508 {AMTVSRD, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0},
509 {AMTVSRD, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0},
510
511 /* VSX logical */
512 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */
513 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */
514
515 /* VSX select */
516 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */
517
518 /* VSX merge */
519 {AXXMRGHW, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */
520
521 /* VSX splat */
522 {AXXSPLTW, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */
523 {AXXSPLTIB, C_SCON, C_NONE, C_NONE, C_VSREG, 100, 4, 0}, /* vsx splat, xx2-form */
524
525 /* VSX permute */
526 {AXXPERM, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */
527
528 /* VSX shift */
529 {AXXSLDWI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */
530
531 /* VSX reverse bytes */
532 {AXXBRQ, C_VSREG, C_NONE, C_NONE, C_VSREG, 101, 4, 0}, /* vsx reverse bytes */
533
534 /* VSX scalar FP-FP conversion */
535 {AXSCVDPSP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */
536
537 /* VSX vector FP-FP conversion */
538 {AXVCVDPSP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */
539
540 /* VSX scalar FP-integer conversion */
541 {AXSCVDPSXDS, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */
542
543 /* VSX scalar integer-FP conversion */
544 {AXSCVSXDDP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */
545
546 /* VSX vector FP-integer conversion */
547 {AXVCVDPSXDS, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */
548
549 /* VSX vector integer-FP conversion */
550 {AXVCVSXDDP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */
551
552 /* 64-bit special registers */
553 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
554 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0},
555 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
556 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
557 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
558 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0},
559 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0},
560 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
561
562 /* 32-bit special registers (gloss over sign-extension or not?) */
563 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
564 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
565 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
566 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
567 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
568 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
569 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
570 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
571 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
572 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
573 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0},
574 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0},
575 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0},
576 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0},
577 {AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0},
578 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
579 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
580 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
581 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0},
582 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0},
583 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0},
584 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0},
585 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0},
586 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0},
587 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0},
588 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0},
589 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0},
590 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0},
591 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0},
592 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0},
593 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0},
594 {ADCBF, C_SOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0},
595 {ADCBF, C_ZOREG, C_REG, C_NONE, C_SCON, 43, 4, 0},
596 {ADCBF, C_SOREG, C_NONE, C_NONE, C_SCON, 43, 4, 0},
597 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
598 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0},
599 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
600 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
601 {ALDAR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
602 {ALDAR, C_ZOREG, C_NONE, C_ANDCON, C_REG, 45, 4, 0},
603 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0},
604 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0},
605 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0},
606 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0},
607 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0},
608 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
609 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0},
610 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
611 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0},
612 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0},
613 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0},
614 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0},
615 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0},
616 {obj.ANOP, C_LCON, C_NONE, C_NONE, C_NONE, 0, 0, 0}, // NOP operand variations added for #40689
617 {obj.ANOP, C_REG, C_NONE, C_NONE, C_NONE, 0, 0, 0}, // to preserve previous behavior
618 {obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, 0, 0, 0},
619 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL
620 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL
621 {obj.APCALIGN, C_LCON, C_NONE, C_NONE, C_NONE, 0, 0, 0}, // align code
622
623 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0},
624 }
625
626 var oprange [ALAST & obj.AMask][]Optab
627
628 var xcmp [C_NCLASS][C_NCLASS]bool
629
630 // padding bytes to add to align code as requested
631 func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
632 // For 16 and 32 byte alignment, there is a tradeoff
633 // between aligning the code and adding too many NOPs.
634 switch a {
635 case 8:
636 if pc&7 != 0 {
637 return 4
638 }
639 case 16:
640 // Align to 16 bytes if possible but add at
641 // most 2 NOPs.
642 switch pc & 15 {
643 case 4, 12:
644 return 4
645 case 8:
646 return 8
647 }
648 case 32:
649 // Align to 32 bytes if possible but add at
650 // most 3 NOPs.
651 switch pc & 31 {
652 case 4, 20:
653 return 12
654 case 8, 24:
655 return 8
656 case 12, 28:
657 return 4
658 }
659 // When 32 byte alignment is requested on Linux,
660 // promote the function's alignment to 32. On AIX
661 // the function alignment is not changed which might
662 // result in 16 byte alignment but that is still fine.
663 // TODO: alignment on AIX
664 if ctxt.Headtype != objabi.Haix && cursym.Func.Align < 32 {
665 cursym.Func.Align = 32
666 }
667 default:
668 ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
669 }
670 return 0
671 }
672
673 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
674 p := cursym.Func.Text
675 if p == nil || p.Link == nil { // handle external functions and ELF section symbols
676 return
677 }
678
679 if oprange[AANDN&obj.AMask] == nil {
680 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
681 }
682
683 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
684
685 pc := int64(0)
686 p.Pc = pc
687
688 var m int
689 var o *Optab
690 for p = p.Link; p != nil; p = p.Link {
691 p.Pc = pc
692 o = c.oplook(p)
693 m = int(o.size)
694 if m == 0 {
695 if p.As == obj.APCALIGN {
696 a := c.vregoff(&p.From)
697 m = addpad(pc, a, ctxt, cursym)
698 } else {
699 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
700 ctxt.Diag("zero-width instruction\n%v", p)
701 }
702 continue
703 }
704 }
705 pc += int64(m)
706 }
707
708 c.cursym.Size = pc
709
710 /*
711 * if any procedure is large enough to
712 * generate a large SBRA branch, then
713 * generate extra passes putting branches
714 * around jmps to fix. this is rare.
715 */
716 bflag := 1
717
718 var otxt int64
719 var q *obj.Prog
720 for bflag != 0 {
721 bflag = 0
722 pc = 0
723 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link {
724 p.Pc = pc
725 o = c.oplook(p)
726
727 // very large conditional branches
728 if (o.type_ == 16 || o.type_ == 17) && p.To.Target() != nil {
729 otxt = p.To.Target().Pc - pc
730 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
731 q = c.newprog()
732 q.Link = p.Link
733 p.Link = q
734 q.As = ABR
735 q.To.Type = obj.TYPE_BRANCH
736 q.To.SetTarget(p.To.Target())
737 p.To.SetTarget(q)
738 q = c.newprog()
739 q.Link = p.Link
740 p.Link = q
741 q.As = ABR
742 q.To.Type = obj.TYPE_BRANCH
743 q.To.SetTarget(q.Link.Link)
744
745 //addnop(p->link);
746 //addnop(p);
747 bflag = 1
748 }
749 }
750
751 m = int(o.size)
752 if m == 0 {
753 if p.As == obj.APCALIGN {
754 a := c.vregoff(&p.From)
755 m = addpad(pc, a, ctxt, cursym)
756 } else {
757 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
758 ctxt.Diag("zero-width instruction\n%v", p)
759 }
760 continue
761 }
762 }
763
764 pc += int64(m)
765 }
766
767 c.cursym.Size = pc
768 }
769
770 if r := pc & funcAlignMask; r != 0 {
771 pc += funcAlign - r
772 }
773
774 c.cursym.Size = pc
775
776 /*
777 * lay out the code, emitting code and data relocations.
778 */
779
780 c.cursym.Grow(c.cursym.Size)
781
782 bp := c.cursym.P
783 var i int32
784 var out [6]uint32
785 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link {
786 c.pc = p.Pc
787 o = c.oplook(p)
788 if int(o.size) > 4*len(out) {
789 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
790 }
791 // asmout is not set up to add large amounts of padding
792 if o.type_ == 0 && p.As == obj.APCALIGN {
793 pad := LOP_RRR(OP_OR, REGZERO, REGZERO, REGZERO)
794 aln := c.vregoff(&p.From)
795 v := addpad(p.Pc, aln, c.ctxt, c.cursym)
796 if v > 0 {
797 // Same padding instruction for all
798 for i = 0; i < int32(v/4); i++ {
799 c.ctxt.Arch.ByteOrder.PutUint32(bp, pad)
800 bp = bp[4:]
801 }
802 }
803 } else {
804 c.asmout(p, o, out[:])
805 for i = 0; i < int32(o.size/4); i++ {
806 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
807 bp = bp[4:]
808 }
809 }
810 }
811 }
812
813 func isint32(v int64) bool {
814 return int64(int32(v)) == v
815 }
816
817 func isuint32(v uint64) bool {
818 return uint64(uint32(v)) == v
819 }
820
821 func (c *ctxt9) aclass(a *obj.Addr) int {
822 switch a.Type {
823 case obj.TYPE_NONE:
824 return C_NONE
825
826 case obj.TYPE_REG:
827 if REG_R0 <= a.Reg && a.Reg <= REG_R31 {
828 return C_REG
829 }
830 if REG_F0 <= a.Reg && a.Reg <= REG_F31 {
831 return C_FREG
832 }
833 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
834 return C_VREG
835 }
836 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 {
837 return C_VSREG
838 }
839 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR {
840 return C_CREG
841 }
842 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 {
843 switch a.Reg {
844 case REG_LR:
845 return C_LR
846
847 case REG_XER:
848 return C_XER
849
850 case REG_CTR:
851 return C_CTR
852 }
853
854 return C_SPR
855 }
856
857 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 {
858 return C_SPR
859 }
860 if a.Reg == REG_FPSCR {
861 return C_FPSCR
862 }
863 if a.Reg == REG_MSR {
864 return C_MSR
865 }
866 return C_GOK
867
868 case obj.TYPE_MEM:
869 switch a.Name {
870 case obj.NAME_EXTERN,
871 obj.NAME_STATIC:
872 if a.Sym == nil {
873 break
874 }
875 c.instoffset = a.Offset
876 if a.Sym != nil { // use relocation
877 if a.Sym.Type == objabi.STLSBSS {
878 if c.ctxt.Flag_shared {
879 return C_TLS_IE
880 } else {
881 return C_TLS_LE
882 }
883 }
884 return C_ADDR
885 }
886 return C_LEXT
887
888 case obj.NAME_GOTREF:
889 return C_GOTADDR
890
891 case obj.NAME_TOCREF:
892 return C_TOCADDR
893
894 case obj.NAME_AUTO:
895 c.instoffset = int64(c.autosize) + a.Offset
896 if c.instoffset >= -BIG && c.instoffset < BIG {
897 return C_SAUTO
898 }
899 return C_LAUTO
900
901 case obj.NAME_PARAM:
902 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
903 if c.instoffset >= -BIG && c.instoffset < BIG {
904 return C_SAUTO
905 }
906 return C_LAUTO
907
908 case obj.NAME_NONE:
909 c.instoffset = a.Offset
910 if c.instoffset == 0 {
911 return C_ZOREG
912 }
913 if c.instoffset >= -BIG && c.instoffset < BIG {
914 return C_SOREG
915 }
916 return C_LOREG
917 }
918
919 return C_GOK
920
921 case obj.TYPE_TEXTSIZE:
922 return C_TEXTSIZE
923
924 case obj.TYPE_FCONST:
925 // The only cases where FCONST will occur are with float64 +/- 0.
926 // All other float constants are generated in memory.
927 f64 := a.Val.(float64)
928 if f64 == 0 {
929 if math.Signbit(f64) {
930 return C_ADDCON
931 }
932 return C_ZCON
933 }
934 log.Fatalf("Unexpected nonzero FCONST operand %v", a)
935
936 case obj.TYPE_CONST,
937 obj.TYPE_ADDR:
938 switch a.Name {
939 case obj.NAME_NONE:
940 c.instoffset = a.Offset
941 if a.Reg != 0 {
942 if -BIG <= c.instoffset && c.instoffset <= BIG {
943 return C_SACON
944 }
945 if isint32(c.instoffset) {
946 return C_LACON
947 }
948 return C_DACON
949 }
950
951 case obj.NAME_EXTERN,
952 obj.NAME_STATIC:
953 s := a.Sym
954 if s == nil {
955 return C_GOK
956 }
957
958 c.instoffset = a.Offset
959
960 /* not sure why this barfs */
961 return C_LCON
962
963 case obj.NAME_AUTO:
964 c.instoffset = int64(c.autosize) + a.Offset
965 if c.instoffset >= -BIG && c.instoffset < BIG {
966 return C_SACON
967 }
968 return C_LACON
969
970 case obj.NAME_PARAM:
971 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
972 if c.instoffset >= -BIG && c.instoffset < BIG {
973 return C_SACON
974 }
975 return C_LACON
976
977 default:
978 return C_GOK
979 }
980
981 if c.instoffset >= 0 {
982 if c.instoffset == 0 {
983 return C_ZCON
984 }
985 if c.instoffset <= 0x7fff {
986 return C_SCON
987 }
988 if c.instoffset <= 0xffff {
989 return C_ANDCON
990 }
991 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */
992 return C_UCON
993 }
994 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
995 return C_LCON
996 }
997 return C_DCON
998 }
999
1000 if c.instoffset >= -0x8000 {
1001 return C_ADDCON
1002 }
1003 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
1004 return C_UCON
1005 }
1006 if isint32(c.instoffset) {
1007 return C_LCON
1008 }
1009 return C_DCON
1010
1011 case obj.TYPE_BRANCH:
1012 if a.Sym != nil && c.ctxt.Flag_dynlink {
1013 return C_LBRAPIC
1014 }
1015 return C_SBRA
1016 }
1017
1018 return C_GOK
1019 }
1020
1021 func prasm(p *obj.Prog) {
1022 fmt.Printf("%v\n", p)
1023 }
1024
1025 func (c *ctxt9) oplook(p *obj.Prog) *Optab {
1026 a1 := int(p.Optab)
1027 if a1 != 0 {
1028 return &optab[a1-1]
1029 }
1030 a1 = int(p.From.Class)
1031 if a1 == 0 {
1032 a1 = c.aclass(&p.From) + 1
1033 p.From.Class = int8(a1)
1034 }
1035
1036 a1--
1037 a3 := C_NONE + 1
1038 if p.GetFrom3() != nil {
1039 a3 = int(p.GetFrom3().Class)
1040 if a3 == 0 {
1041 a3 = c.aclass(p.GetFrom3()) + 1
1042 p.GetFrom3().Class = int8(a3)
1043 }
1044 }
1045
1046 a3--
1047 a4 := int(p.To.Class)
1048 if a4 == 0 {
1049 a4 = c.aclass(&p.To) + 1
1050 p.To.Class = int8(a4)
1051 }
1052
1053 a4--
1054 a2 := C_NONE
1055 if p.Reg != 0 {
1056 if REG_R0 <= p.Reg && p.Reg <= REG_R31 {
1057 a2 = C_REG
1058 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 {
1059 a2 = C_VREG
1060 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 {
1061 a2 = C_VSREG
1062 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 {
1063 a2 = C_FREG
1064 }
1065 }
1066
1067 // c.ctxt.Logf("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4)
1068 ops := oprange[p.As&obj.AMask]
1069 c1 := &xcmp[a1]
1070 c3 := &xcmp[a3]
1071 c4 := &xcmp[a4]
1072 for i := range ops {
1073 op := &ops[i]
1074 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] {
1075 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1076 return op
1077 }
1078 }
1079
1080 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4))
1081 prasm(p)
1082 if ops == nil {
1083 ops = optab
1084 }
1085 return &ops[0]
1086 }
1087
1088 func cmp(a int, b int) bool {
1089 if a == b {
1090 return true
1091 }
1092 switch a {
1093 case C_LCON:
1094 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
1095 return true
1096 }
1097
1098 case C_ADDCON:
1099 if b == C_ZCON || b == C_SCON {
1100 return true
1101 }
1102
1103 case C_ANDCON:
1104 if b == C_ZCON || b == C_SCON {
1105 return true
1106 }
1107
1108 case C_SPR:
1109 if b == C_LR || b == C_XER || b == C_CTR {
1110 return true
1111 }
1112
1113 case C_UCON:
1114 if b == C_ZCON {
1115 return true
1116 }
1117
1118 case C_SCON:
1119 if b == C_ZCON {
1120 return true
1121 }
1122
1123 case C_LACON:
1124 if b == C_SACON {
1125 return true
1126 }
1127
1128 case C_LBRA:
1129 if b == C_SBRA {
1130 return true
1131 }
1132
1133 case C_LEXT:
1134 if b == C_SEXT {
1135 return true
1136 }
1137
1138 case C_LAUTO:
1139 if b == C_SAUTO {
1140 return true
1141 }
1142
1143 case C_REG:
1144 if b == C_ZCON {
1145 return r0iszero != 0 /*TypeKind(100016)*/
1146 }
1147
1148 case C_LOREG:
1149 if b == C_ZOREG || b == C_SOREG {
1150 return true
1151 }
1152
1153 case C_SOREG:
1154 if b == C_ZOREG {
1155 return true
1156 }
1157
1158 case C_ANY:
1159 return true
1160 }
1161
1162 return false
1163 }
1164
1165 type ocmp []Optab
1166
1167 func (x ocmp) Len() int {
1168 return len(x)
1169 }
1170
1171 func (x ocmp) Swap(i, j int) {
1172 x[i], x[j] = x[j], x[i]
1173 }
1174
1175 // Used when sorting the optab. Sorting is
1176 // done in a way so that the best choice of
1177 // opcode/operand combination is considered first.
1178 func (x ocmp) Less(i, j int) bool {
1179 p1 := &x[i]
1180 p2 := &x[j]
1181 n := int(p1.as) - int(p2.as)
1182 // same opcode
1183 if n != 0 {
1184 return n < 0
1185 }
1186 // Consider those that generate fewer
1187 // instructions first.
1188 n = int(p1.size) - int(p2.size)
1189 if n != 0 {
1190 return n < 0
1191 }
1192 // operand order should match
1193 // better choices first
1194 n = int(p1.a1) - int(p2.a1)
1195 if n != 0 {
1196 return n < 0
1197 }
1198 n = int(p1.a2) - int(p2.a2)
1199 if n != 0 {
1200 return n < 0
1201 }
1202 n = int(p1.a3) - int(p2.a3)
1203 if n != 0 {
1204 return n < 0
1205 }
1206 n = int(p1.a4) - int(p2.a4)
1207 if n != 0 {
1208 return n < 0
1209 }
1210 return false
1211 }
1212
1213 // Add an entry to the opcode table for
1214 // a new opcode b0 with the same operand combinations
1215 // as opcode a.
1216 func opset(a, b0 obj.As) {
1217 oprange[a&obj.AMask] = oprange[b0]
1218 }
1219
1220 // Build the opcode table
1221 func buildop(ctxt *obj.Link) {
1222 if oprange[AANDN&obj.AMask] != nil {
1223 // Already initialized; stop now.
1224 // This happens in the cmd/asm tests,
1225 // each of which re-initializes the arch.
1226 return
1227 }
1228
1229 var n int
1230
1231 for i := 0; i < C_NCLASS; i++ {
1232 for n = 0; n < C_NCLASS; n++ {
1233 if cmp(n, i) {
1234 xcmp[i][n] = true
1235 }
1236 }
1237 }
1238 for n = 0; optab[n].as != obj.AXXX; n++ {
1239 }
1240 sort.Sort(ocmp(optab[:n]))
1241 for i := 0; i < n; i++ {
1242 r := optab[i].as
1243 r0 := r & obj.AMask
1244 start := i
1245 for optab[i].as == r {
1246 i++
1247 }
1248 oprange[r0] = optab[start:i]
1249 i--
1250
1251 switch r {
1252 default:
1253 ctxt.Diag("unknown op in build: %v", r)
1254 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
1255
1256 case ADCBF: /* unary indexed: op (b+a); op (b) */
1257 opset(ADCBI, r0)
1258
1259 opset(ADCBST, r0)
1260 opset(ADCBT, r0)
1261 opset(ADCBTST, r0)
1262 opset(ADCBZ, r0)
1263 opset(AICBI, r0)
1264
1265 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */
1266 opset(ASTWCCC, r0)
1267 opset(ASTHCCC, r0)
1268 opset(ASTBCCC, r0)
1269 opset(ASTDCCC, r0)
1270
1271 case AREM: /* macro */
1272 opset(AREM, r0)
1273
1274 case AREMU:
1275 opset(AREMU, r0)
1276
1277 case AREMD:
1278 opset(AREMDU, r0)
1279
1280 case ADIVW: /* op Rb[,Ra],Rd */
1281 opset(AMULHW, r0)
1282
1283 opset(AMULHWCC, r0)
1284 opset(AMULHWU, r0)
1285 opset(AMULHWUCC, r0)
1286 opset(AMULLWCC, r0)
1287 opset(AMULLWVCC, r0)
1288 opset(AMULLWV, r0)
1289 opset(ADIVWCC, r0)
1290 opset(ADIVWV, r0)
1291 opset(ADIVWVCC, r0)
1292 opset(ADIVWU, r0)
1293 opset(ADIVWUCC, r0)
1294 opset(ADIVWUV, r0)
1295 opset(ADIVWUVCC, r0)
1296 opset(AMODUD, r0)
1297 opset(AMODUW, r0)
1298 opset(AMODSD, r0)
1299 opset(AMODSW, r0)
1300 opset(AADDCC, r0)
1301 opset(AADDCV, r0)
1302 opset(AADDCVCC, r0)
1303 opset(AADDV, r0)
1304 opset(AADDVCC, r0)
1305 opset(AADDE, r0)
1306 opset(AADDECC, r0)
1307 opset(AADDEV, r0)
1308 opset(AADDEVCC, r0)
1309 opset(AMULHD, r0)
1310 opset(AMULHDCC, r0)
1311 opset(AMULHDU, r0)
1312 opset(AMULHDUCC, r0)
1313 opset(AMULLD, r0)
1314 opset(AMULLDCC, r0)
1315 opset(AMULLDVCC, r0)
1316 opset(AMULLDV, r0)
1317 opset(ADIVD, r0)
1318 opset(ADIVDCC, r0)
1319 opset(ADIVDE, r0)
1320 opset(ADIVDEU, r0)
1321 opset(ADIVDECC, r0)
1322 opset(ADIVDEUCC, r0)
1323 opset(ADIVDVCC, r0)
1324 opset(ADIVDV, r0)
1325 opset(ADIVDU, r0)
1326 opset(ADIVDUV, r0)
1327 opset(ADIVDUVCC, r0)
1328 opset(ADIVDUCC, r0)
1329
1330 case ACRAND:
1331 opset(ACRANDN, r0)
1332 opset(ACREQV, r0)
1333 opset(ACRNAND, r0)
1334 opset(ACRNOR, r0)
1335 opset(ACROR, r0)
1336 opset(ACRORN, r0)
1337 opset(ACRXOR, r0)
1338
1339 case APOPCNTD: /* popcntd, popcntw, popcntb, cnttzw, cnttzd */
1340 opset(APOPCNTW, r0)
1341 opset(APOPCNTB, r0)
1342 opset(ACNTTZW, r0)
1343 opset(ACNTTZWCC, r0)
1344 opset(ACNTTZD, r0)
1345 opset(ACNTTZDCC, r0)
1346
1347 case ACOPY: /* copy, paste. */
1348 opset(APASTECC, r0)
1349
1350 case AMADDHD: /* maddhd, maddhdu, maddld */
1351 opset(AMADDHDU, r0)
1352 opset(AMADDLD, r0)
1353
1354 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */
1355 opset(AMOVH, r0)
1356 opset(AMOVHZ, r0)
1357
1358 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */
1359 opset(AMOVHU, r0)
1360
1361 opset(AMOVHZU, r0)
1362 opset(AMOVWU, r0)
1363 opset(AMOVWZU, r0)
1364 opset(AMOVDU, r0)
1365 opset(AMOVMW, r0)
1366
1367 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */
1368 opset(ALVEBX, r0)
1369 opset(ALVEHX, r0)
1370 opset(ALVEWX, r0)
1371 opset(ALVX, r0)
1372 opset(ALVXL, r0)
1373 opset(ALVSL, r0)
1374 opset(ALVSR, r0)
1375
1376 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */
1377 opset(ASTVEBX, r0)
1378 opset(ASTVEHX, r0)
1379 opset(ASTVEWX, r0)
1380 opset(ASTVX, r0)
1381 opset(ASTVXL, r0)
1382
1383 case AVAND: /* vand, vandc, vnand */
1384 opset(AVAND, r0)
1385 opset(AVANDC, r0)
1386 opset(AVNAND, r0)
1387
1388 case AVMRGOW: /* vmrgew, vmrgow */
1389 opset(AVMRGEW, r0)
1390
1391 case AVOR: /* vor, vorc, vxor, vnor, veqv */
1392 opset(AVOR, r0)
1393 opset(AVORC, r0)
1394 opset(AVXOR, r0)
1395 opset(AVNOR, r0)
1396 opset(AVEQV, r0)
1397
1398 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */
1399 opset(AVADDUBM, r0)
1400 opset(AVADDUHM, r0)
1401 opset(AVADDUWM, r0)
1402 opset(AVADDUDM, r0)
1403 opset(AVADDUQM, r0)
1404
1405 case AVADDCU: /* vaddcuq, vaddcuw */
1406 opset(AVADDCUQ, r0)
1407 opset(AVADDCUW, r0)
1408
1409 case AVADDUS: /* vaddubs, vadduhs, vadduws */
1410 opset(AVADDUBS, r0)
1411 opset(AVADDUHS, r0)
1412 opset(AVADDUWS, r0)
1413
1414 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */
1415 opset(AVADDSBS, r0)
1416 opset(AVADDSHS, r0)
1417 opset(AVADDSWS, r0)
1418
1419 case AVADDE: /* vaddeuqm, vaddecuq */
1420 opset(AVADDEUQM, r0)
1421 opset(AVADDECUQ, r0)
1422
1423 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */
1424 opset(AVSUBUBM, r0)
1425 opset(AVSUBUHM, r0)
1426 opset(AVSUBUWM, r0)
1427 opset(AVSUBUDM, r0)
1428 opset(AVSUBUQM, r0)
1429
1430 case AVSUBCU: /* vsubcuq, vsubcuw */
1431 opset(AVSUBCUQ, r0)
1432 opset(AVSUBCUW, r0)
1433
1434 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */
1435 opset(AVSUBUBS, r0)
1436 opset(AVSUBUHS, r0)
1437 opset(AVSUBUWS, r0)
1438
1439 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */
1440 opset(AVSUBSBS, r0)
1441 opset(AVSUBSHS, r0)
1442 opset(AVSUBSWS, r0)
1443
1444 case AVSUBE: /* vsubeuqm, vsubecuq */
1445 opset(AVSUBEUQM, r0)
1446 opset(AVSUBECUQ, r0)
1447
1448 case AVMULESB: /* vmulesb, vmulosb, vmuleub, vmuloub, vmulosh, vmulouh, vmulesw, vmulosw, vmuleuw, vmulouw, vmuluwm */
1449 opset(AVMULOSB, r0)
1450 opset(AVMULEUB, r0)
1451 opset(AVMULOUB, r0)
1452 opset(AVMULESH, r0)
1453 opset(AVMULOSH, r0)
1454 opset(AVMULEUH, r0)
1455 opset(AVMULOUH, r0)
1456 opset(AVMULESW, r0)
1457 opset(AVMULOSW, r0)
1458 opset(AVMULEUW, r0)
1459 opset(AVMULOUW, r0)
1460 opset(AVMULUWM, r0)
1461 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */
1462 opset(AVPMSUMB, r0)
1463 opset(AVPMSUMH, r0)
1464 opset(AVPMSUMW, r0)
1465 opset(AVPMSUMD, r0)
1466
1467 case AVR: /* vrlb, vrlh, vrlw, vrld */
1468 opset(AVRLB, r0)
1469 opset(AVRLH, r0)
1470 opset(AVRLW, r0)
1471 opset(AVRLD, r0)
1472
1473 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */
1474 opset(AVSLB, r0)
1475 opset(AVSLH, r0)
1476 opset(AVSLW, r0)
1477 opset(AVSL, r0)
1478 opset(AVSLO, r0)
1479 opset(AVSRB, r0)
1480 opset(AVSRH, r0)
1481 opset(AVSRW, r0)
1482 opset(AVSR, r0)
1483 opset(AVSRO, r0)
1484 opset(AVSLD, r0)
1485 opset(AVSRD, r0)
1486
1487 case AVSA: /* vsrab, vsrah, vsraw, vsrad */
1488 opset(AVSRAB, r0)
1489 opset(AVSRAH, r0)
1490 opset(AVSRAW, r0)
1491 opset(AVSRAD, r0)
1492
1493 case AVSOI: /* vsldoi */
1494 opset(AVSLDOI, r0)
1495
1496 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */
1497 opset(AVCLZB, r0)
1498 opset(AVCLZH, r0)
1499 opset(AVCLZW, r0)
1500 opset(AVCLZD, r0)
1501
1502 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */
1503 opset(AVPOPCNTB, r0)
1504 opset(AVPOPCNTH, r0)
1505 opset(AVPOPCNTW, r0)
1506 opset(AVPOPCNTD, r0)
1507
1508 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */
1509 opset(AVCMPEQUB, r0)
1510 opset(AVCMPEQUBCC, r0)
1511 opset(AVCMPEQUH, r0)
1512 opset(AVCMPEQUHCC, r0)
1513 opset(AVCMPEQUW, r0)
1514 opset(AVCMPEQUWCC, r0)
1515 opset(AVCMPEQUD, r0)
1516 opset(AVCMPEQUDCC, r0)
1517
1518 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */
1519 opset(AVCMPGTUB, r0)
1520 opset(AVCMPGTUBCC, r0)
1521 opset(AVCMPGTUH, r0)
1522 opset(AVCMPGTUHCC, r0)
1523 opset(AVCMPGTUW, r0)
1524 opset(AVCMPGTUWCC, r0)
1525 opset(AVCMPGTUD, r0)
1526 opset(AVCMPGTUDCC, r0)
1527 opset(AVCMPGTSB, r0)
1528 opset(AVCMPGTSBCC, r0)
1529 opset(AVCMPGTSH, r0)
1530 opset(AVCMPGTSHCC, r0)
1531 opset(AVCMPGTSW, r0)
1532 opset(AVCMPGTSWCC, r0)
1533 opset(AVCMPGTSD, r0)
1534 opset(AVCMPGTSDCC, r0)
1535
1536 case AVCMPNEZB: /* vcmpnezb[.] */
1537 opset(AVCMPNEZBCC, r0)
1538 opset(AVCMPNEB, r0)
1539 opset(AVCMPNEBCC, r0)
1540 opset(AVCMPNEH, r0)
1541 opset(AVCMPNEHCC, r0)
1542 opset(AVCMPNEW, r0)
1543 opset(AVCMPNEWCC, r0)
1544
1545 case AVPERM: /* vperm */
1546 opset(AVPERMXOR, r0)
1547 opset(AVPERMR, r0)
1548
1549 case AVBPERMQ: /* vbpermq, vbpermd */
1550 opset(AVBPERMD, r0)
1551
1552 case AVSEL: /* vsel */
1553 opset(AVSEL, r0)
1554
1555 case AVSPLTB: /* vspltb, vsplth, vspltw */
1556 opset(AVSPLTH, r0)
1557 opset(AVSPLTW, r0)
1558
1559 case AVSPLTISB: /* vspltisb, vspltish, vspltisw */
1560 opset(AVSPLTISH, r0)
1561 opset(AVSPLTISW, r0)
1562
1563 case AVCIPH: /* vcipher, vcipherlast */
1564 opset(AVCIPHER, r0)
1565 opset(AVCIPHERLAST, r0)
1566
1567 case AVNCIPH: /* vncipher, vncipherlast */
1568 opset(AVNCIPHER, r0)
1569 opset(AVNCIPHERLAST, r0)
1570
1571 case AVSBOX: /* vsbox */
1572 opset(AVSBOX, r0)
1573
1574 case AVSHASIGMA: /* vshasigmaw, vshasigmad */
1575 opset(AVSHASIGMAW, r0)
1576 opset(AVSHASIGMAD, r0)
1577
1578 case ALXVD2X: /* lxvd2x, lxvdsx, lxvw4x, lxvh8x, lxvb16x */
1579 opset(ALXVDSX, r0)
1580 opset(ALXVW4X, r0)
1581 opset(ALXVH8X, r0)
1582 opset(ALXVB16X, r0)
1583
1584 case ALXV: /* lxv */
1585 opset(ALXV, r0)
1586
1587 case ALXVL: /* lxvl, lxvll, lxvx */
1588 opset(ALXVLL, r0)
1589 opset(ALXVX, r0)
1590
1591 case ASTXVD2X: /* stxvd2x, stxvdsx, stxvw4x, stxvh8x, stxvb16x */
1592 opset(ASTXVW4X, r0)
1593 opset(ASTXVH8X, r0)
1594 opset(ASTXVB16X, r0)
1595
1596 case ASTXV: /* stxv */
1597 opset(ASTXV, r0)
1598
1599 case ASTXVL: /* stxvl, stxvll, stvx */
1600 opset(ASTXVLL, r0)
1601 opset(ASTXVX, r0)
1602
1603 case ALXSDX: /* lxsdx */
1604 opset(ALXSDX, r0)
1605
1606 case ASTXSDX: /* stxsdx */
1607 opset(ASTXSDX, r0)
1608
1609 case ALXSIWAX: /* lxsiwax, lxsiwzx */
1610 opset(ALXSIWZX, r0)
1611
1612 case ASTXSIWX: /* stxsiwx */
1613 opset(ASTXSIWX, r0)
1614
1615 case AMFVSRD: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */
1616 opset(AMFFPRD, r0)
1617 opset(AMFVRD, r0)
1618 opset(AMFVSRWZ, r0)
1619 opset(AMFVSRLD, r0)
1620
1621 case AMTVSRD: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */
1622 opset(AMTFPRD, r0)
1623 opset(AMTVRD, r0)
1624 opset(AMTVSRWA, r0)
1625 opset(AMTVSRWZ, r0)
1626 opset(AMTVSRDD, r0)
1627 opset(AMTVSRWS, r0)
1628
1629 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */
1630 opset(AXXLANDC, r0)
1631 opset(AXXLEQV, r0)
1632 opset(AXXLNAND, r0)
1633
1634 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */
1635 opset(AXXLORC, r0)
1636 opset(AXXLNOR, r0)
1637 opset(AXXLORQ, r0)
1638 opset(AXXLXOR, r0)
1639
1640 case AXXSEL: /* xxsel */
1641 opset(AXXSEL, r0)
1642
1643 case AXXMRGHW: /* xxmrghw, xxmrglw */
1644 opset(AXXMRGLW, r0)
1645
1646 case AXXSPLTW: /* xxspltw */
1647 opset(AXXSPLTW, r0)
1648
1649 case AXXSPLTIB: /* xxspltib */
1650 opset(AXXSPLTIB, r0)
1651
1652 case AXXPERM: /* xxpermdi */
1653 opset(AXXPERM, r0)
1654
1655 case AXXSLDWI: /* xxsldwi */
1656 opset(AXXPERMDI, r0)
1657 opset(AXXSLDWI, r0)
1658
1659 case AXXBRQ: /* xxbrq, xxbrd, xxbrw, xxbrh */
1660 opset(AXXBRD, r0)
1661 opset(AXXBRW, r0)
1662 opset(AXXBRH, r0)
1663
1664 case AXSCVDPSP: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */
1665 opset(AXSCVSPDP, r0)
1666 opset(AXSCVDPSPN, r0)
1667 opset(AXSCVSPDPN, r0)
1668
1669 case AXVCVDPSP: /* xvcvdpsp, xvcvspdp */
1670 opset(AXVCVSPDP, r0)
1671
1672 case AXSCVDPSXDS: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */
1673 opset(AXSCVDPSXWS, r0)
1674 opset(AXSCVDPUXDS, r0)
1675 opset(AXSCVDPUXWS, r0)
1676
1677 case AXSCVSXDDP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */
1678 opset(AXSCVUXDDP, r0)
1679 opset(AXSCVSXDSP, r0)
1680 opset(AXSCVUXDSP, r0)
1681
1682 case AXVCVDPSXDS: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */
1683 opset(AXVCVDPSXDS, r0)
1684 opset(AXVCVDPSXWS, r0)
1685 opset(AXVCVDPUXDS, r0)
1686 opset(AXVCVDPUXWS, r0)
1687 opset(AXVCVSPSXDS, r0)
1688 opset(AXVCVSPSXWS, r0)
1689 opset(AXVCVSPUXDS, r0)
1690 opset(AXVCVSPUXWS, r0)
1691
1692 case AXVCVSXDDP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */
1693 opset(AXVCVSXWDP, r0)
1694 opset(AXVCVUXDDP, r0)
1695 opset(AXVCVUXWDP, r0)
1696 opset(AXVCVSXDSP, r0)
1697 opset(AXVCVSXWSP, r0)
1698 opset(AXVCVUXDSP, r0)
1699 opset(AXVCVUXWSP, r0)
1700
1701 case AAND: /* logical op Rb,Rs,Ra; no literal */
1702 opset(AANDN, r0)
1703 opset(AANDNCC, r0)
1704 opset(AEQV, r0)
1705 opset(AEQVCC, r0)
1706 opset(ANAND, r0)
1707 opset(ANANDCC, r0)
1708 opset(ANOR, r0)
1709 opset(ANORCC, r0)
1710 opset(AORCC, r0)
1711 opset(AORN, r0)
1712 opset(AORNCC, r0)
1713 opset(AXORCC, r0)
1714
1715 case AADDME: /* op Ra, Rd */
1716 opset(AADDMECC, r0)
1717
1718 opset(AADDMEV, r0)
1719 opset(AADDMEVCC, r0)
1720 opset(AADDZE, r0)
1721 opset(AADDZECC, r0)
1722 opset(AADDZEV, r0)
1723 opset(AADDZEVCC, r0)
1724 opset(ASUBME, r0)
1725 opset(ASUBMECC, r0)
1726 opset(ASUBMEV, r0)
1727 opset(ASUBMEVCC, r0)
1728 opset(ASUBZE, r0)
1729 opset(ASUBZECC, r0)
1730 opset(ASUBZEV, r0)
1731 opset(ASUBZEVCC, r0)
1732
1733 case AADDC:
1734 opset(AADDCCC, r0)
1735
1736 case ABEQ:
1737 opset(ABGE, r0)
1738 opset(ABGT, r0)
1739 opset(ABLE, r0)
1740 opset(ABLT, r0)
1741 opset(ABNE, r0)
1742 opset(ABVC, r0)
1743 opset(ABVS, r0)
1744
1745 case ABR:
1746 opset(ABL, r0)
1747
1748 case ABC:
1749 opset(ABCL, r0)
1750
1751 case AEXTSB: /* op Rs, Ra */
1752 opset(AEXTSBCC, r0)
1753
1754 opset(AEXTSH, r0)
1755 opset(AEXTSHCC, r0)
1756 opset(ACNTLZW, r0)
1757 opset(ACNTLZWCC, r0)
1758 opset(ACNTLZD, r0)
1759 opset(AEXTSW, r0)
1760 opset(AEXTSWCC, r0)
1761 opset(ACNTLZDCC, r0)
1762
1763 case AFABS: /* fop [s,]d */
1764 opset(AFABSCC, r0)
1765
1766 opset(AFNABS, r0)
1767 opset(AFNABSCC, r0)
1768 opset(AFNEG, r0)
1769 opset(AFNEGCC, r0)
1770 opset(AFRSP, r0)
1771 opset(AFRSPCC, r0)
1772 opset(AFCTIW, r0)
1773 opset(AFCTIWCC, r0)
1774 opset(AFCTIWZ, r0)
1775 opset(AFCTIWZCC, r0)
1776 opset(AFCTID, r0)
1777 opset(AFCTIDCC, r0)
1778 opset(AFCTIDZ, r0)
1779 opset(AFCTIDZCC, r0)
1780 opset(AFCFID, r0)
1781 opset(AFCFIDCC, r0)
1782 opset(AFCFIDU, r0)
1783 opset(AFCFIDUCC, r0)
1784 opset(AFCFIDS, r0)
1785 opset(AFCFIDSCC, r0)
1786 opset(AFRES, r0)
1787 opset(AFRESCC, r0)
1788 opset(AFRIM, r0)
1789 opset(AFRIMCC, r0)
1790 opset(AFRIP, r0)
1791 opset(AFRIPCC, r0)
1792 opset(AFRIZ, r0)
1793 opset(AFRIZCC, r0)
1794 opset(AFRIN, r0)
1795 opset(AFRINCC, r0)
1796 opset(AFRSQRTE, r0)
1797 opset(AFRSQRTECC, r0)
1798 opset(AFSQRT, r0)
1799 opset(AFSQRTCC, r0)
1800 opset(AFSQRTS, r0)
1801 opset(AFSQRTSCC, r0)
1802
1803 case AFADD:
1804 opset(AFADDS, r0)
1805 opset(AFADDCC, r0)
1806 opset(AFADDSCC, r0)
1807 opset(AFCPSGN, r0)
1808 opset(AFCPSGNCC, r0)
1809 opset(AFDIV, r0)
1810 opset(AFDIVS, r0)
1811 opset(AFDIVCC, r0)
1812 opset(AFDIVSCC, r0)
1813 opset(AFSUB, r0)
1814 opset(AFSUBS, r0)
1815 opset(AFSUBCC, r0)
1816 opset(AFSUBSCC, r0)
1817
1818 case AFMADD:
1819 opset(AFMADDCC, r0)
1820 opset(AFMADDS, r0)
1821 opset(AFMADDSCC, r0)
1822 opset(AFMSUB, r0)
1823 opset(AFMSUBCC, r0)
1824 opset(AFMSUBS, r0)
1825 opset(AFMSUBSCC, r0)
1826 opset(AFNMADD, r0)
1827 opset(AFNMADDCC, r0)
1828 opset(AFNMADDS, r0)
1829 opset(AFNMADDSCC, r0)
1830 opset(AFNMSUB, r0)
1831 opset(AFNMSUBCC, r0)
1832 opset(AFNMSUBS, r0)
1833 opset(AFNMSUBSCC, r0)
1834 opset(AFSEL, r0)
1835 opset(AFSELCC, r0)
1836
1837 case AFMUL:
1838 opset(AFMULS, r0)
1839 opset(AFMULCC, r0)
1840 opset(AFMULSCC, r0)
1841
1842 case AFCMPO:
1843 opset(AFCMPU, r0)
1844
1845 case AISEL:
1846 opset(AISEL, r0)
1847
1848 case AMTFSB0:
1849 opset(AMTFSB0CC, r0)
1850 opset(AMTFSB1, r0)
1851 opset(AMTFSB1CC, r0)
1852
1853 case ANEG: /* op [Ra,] Rd */
1854 opset(ANEGCC, r0)
1855
1856 opset(ANEGV, r0)
1857 opset(ANEGVCC, r0)
1858
1859 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,R */
1860 opset(AXOR, r0)
1861
1862 case AORIS: /* oris/xoris $uimm,Rs,Ra */
1863 opset(AXORIS, r0)
1864
1865 case ASLW:
1866 opset(ASLWCC, r0)
1867 opset(ASRW, r0)
1868 opset(ASRWCC, r0)
1869 opset(AROTLW, r0)
1870
1871 case ASLD:
1872 opset(ASLDCC, r0)
1873 opset(ASRD, r0)
1874 opset(ASRDCC, r0)
1875 opset(AROTL, r0)
1876
1877 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
1878 opset(ASRAWCC, r0)
1879
1880 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
1881 opset(ASRADCC, r0)
1882
1883 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */
1884 opset(ASUB, r0)
1885
1886 opset(ASUBCC, r0)
1887 opset(ASUBV, r0)
1888 opset(ASUBVCC, r0)
1889 opset(ASUBCCC, r0)
1890 opset(ASUBCV, r0)
1891 opset(ASUBCVCC, r0)
1892 opset(ASUBE, r0)
1893 opset(ASUBECC, r0)
1894 opset(ASUBEV, r0)
1895 opset(ASUBEVCC, r0)
1896
1897 case ASYNC:
1898 opset(AISYNC, r0)
1899 opset(ALWSYNC, r0)
1900 opset(APTESYNC, r0)
1901 opset(ATLBSYNC, r0)
1902
1903 case ARLWMI:
1904 opset(ARLWMICC, r0)
1905 opset(ARLWNM, r0)
1906 opset(ARLWNMCC, r0)
1907 opset(ACLRLSLWI, r0)
1908
1909 case ARLDMI:
1910 opset(ARLDMICC, r0)
1911 opset(ARLDIMI, r0)
1912 opset(ARLDIMICC, r0)
1913
1914 case ARLDC:
1915 opset(ARLDCCC, r0)
1916
1917 case ARLDCL:
1918 opset(ARLDCR, r0)
1919 opset(ARLDCLCC, r0)
1920 opset(ARLDCRCC, r0)
1921
1922 case ARLDICL:
1923 opset(ARLDICLCC, r0)
1924 opset(ARLDICR, r0)
1925 opset(ARLDICRCC, r0)
1926 opset(ARLDIC, r0)
1927 opset(ARLDICCC, r0)
1928 opset(ACLRLSLDI, r0)
1929
1930 case AFMOVD:
1931 opset(AFMOVDCC, r0)
1932 opset(AFMOVDU, r0)
1933 opset(AFMOVS, r0)
1934 opset(AFMOVSU, r0)
1935
1936 case ALDAR:
1937 opset(ALBAR, r0)
1938 opset(ALHAR, r0)
1939 opset(ALWAR, r0)
1940
1941 case ASYSCALL: /* just the op; flow of control */
1942 opset(ARFI, r0)
1943
1944 opset(ARFCI, r0)
1945 opset(ARFID, r0)
1946 opset(AHRFID, r0)
1947
1948 case AMOVHBR:
1949 opset(AMOVWBR, r0)
1950 opset(AMOVDBR, r0)
1951
1952 case ASLBMFEE:
1953 opset(ASLBMFEV, r0)
1954
1955 case ATW:
1956 opset(ATD, r0)
1957
1958 case ATLBIE:
1959 opset(ASLBIE, r0)
1960 opset(ATLBIEL, r0)
1961
1962 case AEIEIO:
1963 opset(ASLBIA, r0)
1964
1965 case ACMP:
1966 opset(ACMPW, r0)
1967
1968 case ACMPU:
1969 opset(ACMPWU, r0)
1970
1971 case ACMPB:
1972 opset(ACMPB, r0)
1973
1974 case AFTDIV:
1975 opset(AFTDIV, r0)
1976
1977 case AFTSQRT:
1978 opset(AFTSQRT, r0)
1979
1980 case AADD,
1981 AADDIS,
1982 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra */
1983 AANDISCC,
1984 AFMOVSX,
1985 AFMOVSZ,
1986 ALSW,
1987 AMOVW,
1988 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */
1989 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */
1990 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */
1991 AMOVB, /* macro: move byte with sign extension */
1992 AMOVBU, /* macro: move byte with sign extension & update */
1993 AMOVFL,
1994 AMULLW,
1995 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */
1996 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */
1997 ASTSW,
1998 ASLBMTE,
1999 AWORD,
2000 ADWORD,
2001 ADARN,
2002 ALDMX,
2003 AVMSUMUDM,
2004 AADDEX,
2005 ACMPEQB,
2006 AECIWX,
2007 obj.ANOP,
2008 obj.ATEXT,
2009 obj.AUNDEF,
2010 obj.AFUNCDATA,
2011 obj.APCALIGN,
2012 obj.APCDATA,
2013 obj.ADUFFZERO,
2014 obj.ADUFFCOPY:
2015 break
2016 }
2017 }
2018 }
2019
2020 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
2021 return o<<26 | xo<<1 | oe<<11
2022 }
2023
2024 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
2025 return o<<26 | xo<<2 | oe<<11
2026 }
2027
2028 func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32 {
2029 return o<<26 | xo<<2 | oe<<16
2030 }
2031
2032 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
2033 return o<<26 | xo<<3 | oe<<11
2034 }
2035
2036 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
2037 return o<<26 | xo<<4 | oe<<11
2038 }
2039
2040 func OPDQ(o uint32, xo uint32, oe uint32) uint32 {
2041 return o<<26 | xo | oe<<4
2042 }
2043
2044 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2045 return o<<26 | xo | oe<<11 | rc&1
2046 }
2047
2048 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2049 return o<<26 | xo | oe<<11 | (rc&1)<<10
2050 }
2051
2052 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2053 return o<<26 | xo<<1 | oe<<10 | rc&1
2054 }
2055
2056 func OPCC(o uint32, xo uint32, rc uint32) uint32 {
2057 return OPVCC(o, xo, 0, rc)
2058 }
2059
2060 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */
2061 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
2062 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
2063 }
2064
2065 /* VX-form 2-register operands, r/none/r */
2066 func AOP_RR(op uint32, d uint32, a uint32) uint32 {
2067 return op | (d&31)<<21 | (a&31)<<11
2068 }
2069
2070 /* VA-form 4-register operands */
2071 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2072 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
2073 }
2074
2075 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2076 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
2077 }
2078
2079 /* VX-form 2-register + UIM operands */
2080 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2081 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
2082 }
2083
2084 /* VX-form 2-register + ST + SIX operands */
2085 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
2086 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
2087 }
2088
2089 /* VA-form 3-register + SHB operands */
2090 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
2091 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
2092 }
2093
2094 /* VX-form 1-register + SIM operands */
2095 func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
2096 return op | (d&31)<<21 | (simm&31)<<16
2097 }
2098
2099 /* XX1-form 3-register operands, 1 VSR operand */
2100 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 {
2101 /* For the XX-form encodings, we need the VSX register number to be exactly */
2102 /* between 0-63, so we can properly set the rightmost bits. */
2103 r := d - REG_VS0
2104 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
2105 }
2106
2107 /* XX2-form 3-register operands, 2 VSR operands */
2108 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 {
2109 xt := d - REG_VS0
2110 xb := b - REG_VS0
2111 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
2112 }
2113
2114 /* XX3-form 3 VSR operands */
2115 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 {
2116 xt := d - REG_VS0
2117 xa := a - REG_VS0
2118 xb := b - REG_VS0
2119 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2120 }
2121
2122 /* XX3-form 3 VSR operands + immediate */
2123 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2124 xt := d - REG_VS0
2125 xa := a - REG_VS0
2126 xb := b - REG_VS0
2127 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2128 }
2129
2130 /* XX4-form, 4 VSR operands */
2131 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2132 xt := d - REG_VS0
2133 xa := a - REG_VS0
2134 xb := b - REG_VS0
2135 xc := c - REG_VS0
2136 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2137 }
2138
2139 /* DQ-form, VSR register, register + offset operands */
2140 func AOP_DQ(op uint32, d uint32, a uint32, b uint32) uint32 {
2141 /* For the DQ-form encodings, we need the VSX register number to be exactly */
2142 /* between 0-63, so we can properly set the SX bit. */
2143 r := d - REG_VS0
2144 /* The EA for this instruction form is (RA) + DQ << 4, where DQ is a 12-bit signed integer. */
2145 /* In order to match the output of the GNU objdump (and make the usage in Go asm easier), the */
2146 /* instruction is called using the sign extended value (i.e. a valid offset would be -32752 or 32752, */
2147 /* not -2047 or 2047), so 'b' needs to be adjusted to the expected 12-bit DQ value. Bear in mind that */
2148 /* bits 0 to 3 in 'dq' need to be zero, otherwise this will generate an illegal instruction. */
2149 /* If in doubt how this instruction form is encoded, refer to ISA 3.0b, pages 492 and 507. */
2150 dq := b >> 4
2151 return op | (r&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (r&32)>>2
2152 }
2153
2154 /* Z23-form, 3-register operands + CY field */
2155 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2156 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<7
2157 }
2158
2159 /* X-form, 3-register operands + EH field */
2160 func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2161 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
2162 }
2163
2164 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
2165 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
2166 }
2167
2168 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
2169 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
2170 }
2171
2172 func OP_BR(op uint32, li uint32, aa uint32) uint32 {
2173 return op | li&0x03FFFFFC | aa<<1
2174 }
2175
2176 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
2177 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
2178 }
2179
2180 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
2181 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
2182 }
2183
2184 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
2185 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
2186 }
2187
2188 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
2189 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
2190 }
2191
2192 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
2193 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
2194 }
2195
2196 const (
2197 /* each rhs is OPVCC(_, _, _, _) */
2198 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
2199 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
2200 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
2201 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0
2202 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0
2203 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0
2204 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0
2205 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0
2206 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0
2207 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0
2208 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
2209 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
2210 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
2211 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0
2212 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
2213 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
2214 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
2215 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
2216 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
2217 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
2218 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0
2219 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0
2220 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
2221 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
2222 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
2223 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0
2224 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0
2225 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0
2226 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0
2227 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0
2228 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
2229 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0
2230 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0
2231 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0
2232 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
2233 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
2234 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0
2235 )
2236
2237 func oclass(a *obj.Addr) int {
2238 return int(a.Class) - 1
2239 }
2240
2241 const (
2242 D_FORM = iota
2243 DS_FORM
2244 )
2245
2246 // This function determines when a non-indexed load or store is D or
2247 // DS form for use in finding the size of the offset field in the instruction.
2248 // The size is needed when setting the offset value in the instruction
2249 // and when generating relocation for that field.
2250 // DS form instructions include: ld, ldu, lwa, std, stdu. All other
2251 // loads and stores with an offset field are D form. This function should
2252 // only be called with the same opcodes as are handled by opstore and opload.
2253 func (c *ctxt9) opform(insn uint32) int {
2254 switch insn {
2255 default:
2256 c.ctxt.Diag("bad insn in loadform: %x", insn)
2257 case OPVCC(58, 0, 0, 0), // ld
2258 OPVCC(58, 0, 0, 1), // ldu
2259 OPVCC(58, 0, 0, 0) | 1<<1, // lwa
2260 OPVCC(62, 0, 0, 0), // std
2261 OPVCC(62, 0, 0, 1): //stdu
2262 return DS_FORM
2263 case OP_ADDI, // add
2264 OPVCC(32, 0, 0, 0), // lwz
2265 OPVCC(33, 0, 0, 0), // lwzu
2266 OPVCC(34, 0, 0, 0), // lbz
2267 OPVCC(35, 0, 0, 0), // lbzu
2268 OPVCC(40, 0, 0, 0), // lhz
2269 OPVCC(41, 0, 0, 0), // lhzu
2270 OPVCC(42, 0, 0, 0), // lha
2271 OPVCC(43, 0, 0, 0), // lhau
2272 OPVCC(46, 0, 0, 0), // lmw
2273 OPVCC(48, 0, 0, 0), // lfs
2274 OPVCC(49, 0, 0, 0), // lfsu
2275 OPVCC(50, 0, 0, 0), // lfd
2276 OPVCC(51, 0, 0, 0), // lfdu
2277 OPVCC(36, 0, 0, 0), // stw
2278 OPVCC(37, 0, 0, 0), // stwu
2279 OPVCC(38, 0, 0, 0), // stb
2280 OPVCC(39, 0, 0, 0), // stbu
2281 OPVCC(44, 0, 0, 0), // sth
2282 OPVCC(45, 0, 0, 0), // sthu
2283 OPVCC(47, 0, 0, 0), // stmw
2284 OPVCC(52, 0, 0, 0), // stfs
2285 OPVCC(53, 0, 0, 0), // stfsu
2286 OPVCC(54, 0, 0, 0), // stfd
2287 OPVCC(55, 0, 0, 0): // stfdu
2288 return D_FORM
2289 }
2290 return 0
2291 }
2292
2293 // Encode instructions and create relocation for accessing s+d according to the
2294 // instruction op with source or destination (as appropriate) register reg.
2295 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) {
2296 if c.ctxt.Headtype == objabi.Haix {
2297 // Every symbol access must be made via a TOC anchor.
2298 c.ctxt.Diag("symbolAccess called for %s", s.Name)
2299 }
2300 var base uint32
2301 form := c.opform(op)
2302 if c.ctxt.Flag_shared {
2303 base = REG_R2
2304 } else {
2305 base = REG_R0
2306 }
2307 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
2308 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
2309 rel := obj.Addrel(c.cursym)
2310 rel.Off = int32(c.pc)
2311 rel.Siz = 8
2312 rel.Sym = s
2313 rel.Add = d
2314 if c.ctxt.Flag_shared {
2315 switch form {
2316 case D_FORM:
2317 rel.Type = objabi.R_ADDRPOWER_TOCREL
2318 case DS_FORM:
2319 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
2320 }
2321
2322 } else {
2323 switch form {
2324 case D_FORM:
2325 rel.Type = objabi.R_ADDRPOWER
2326 case DS_FORM:
2327 rel.Type = objabi.R_ADDRPOWER_DS
2328 }
2329 }
2330 return
2331 }
2332
2333 /*
2334 * 32-bit masks
2335 */
2336 func getmask(m []byte, v uint32) bool {
2337 m[1] = 0
2338 m[0] = m[1]
2339 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */
2340 if getmask(m, ^v) {
2341 i := int(m[0])
2342 m[0] = m[1] + 1
2343 m[1] = byte(i - 1)
2344 return true
2345 }
2346
2347 return false
2348 }
2349
2350 for i := 0; i < 32; i++ {
2351 if v&(1<<uint(31-i)) != 0 {
2352 m[0] = byte(i)
2353 for {
2354 m[1] = byte(i)
2355 i++
2356 if i >= 32 || v&(1<<uint(31-i)) == 0 {
2357 break
2358 }
2359 }
2360
2361 for ; i < 32; i++ {
2362 if v&(1<<uint(31-i)) != 0 {
2363 return false
2364 }
2365 }
2366 return true
2367 }
2368 }
2369
2370 return false
2371 }
2372
2373 func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) {
2374 if !getmask(m, v) {
2375 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p)
2376 }
2377 }
2378
2379 /*
2380 * 64-bit masks (rldic etc)
2381 */
2382 func getmask64(m []byte, v uint64) bool {
2383 m[1] = 0
2384 m[0] = m[1]
2385 for i := 0; i < 64; i++ {
2386 if v&(uint64(1)<<uint(63-i)) != 0 {
2387 m[0] = byte(i)
2388 for {
2389 m[1] = byte(i)
2390 i++
2391 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 {
2392 break
2393 }
2394 }
2395
2396 for ; i < 64; i++ {
2397 if v&(uint64(1)<<uint(63-i)) != 0 {
2398 return false
2399 }
2400 }
2401 return true
2402 }
2403 }
2404
2405 return false
2406 }
2407
2408 func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) {
2409 if !getmask64(m, v) {
2410 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p)
2411 }
2412 }
2413
2414 func loadu32(r int, d int64) uint32 {
2415 v := int32(d >> 16)
2416 if isuint32(uint64(d)) {
2417 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
2418 }
2419 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
2420 }
2421
2422 func high16adjusted(d int32) uint16 {
2423 if d&0x8000 != 0 {
2424 return uint16((d >> 16) + 1)
2425 }
2426 return uint16(d >> 16)
2427 }
2428
2429 func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
2430 o1 := uint32(0)
2431 o2 := uint32(0)
2432 o3 := uint32(0)
2433 o4 := uint32(0)
2434 o5 := uint32(0)
2435
2436 //print("%v => case %d\n", p, o->type);
2437 switch o.type_ {
2438 default:
2439 c.ctxt.Diag("unknown type %d", o.type_)
2440 prasm(p)
2441
2442 case 0: /* pseudo ops */
2443 break
2444
2445 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */
2446 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST {
2447 v := c.regoff(&p.From)
2448 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 {
2449 //nerrors--;
2450 c.ctxt.Diag("literal operation on R0\n%v", p)
2451 }
2452
2453 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v))
2454 break
2455 }
2456
2457 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
2458
2459 case 2: /* int/cr/fp op Rb,[Ra],Rd */
2460 r := int(p.Reg)
2461
2462 if r == 0 {
2463 r = int(p.To.Reg)
2464 }
2465 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2466
2467 case 3: /* mov $soreg/addcon/andcon/ucon, r ==> addis/oris/addi/ori $i,reg',r */
2468 d := c.vregoff(&p.From)
2469
2470 v := int32(d)
2471 r := int(p.From.Reg)
2472 if r == 0 {
2473 r = int(o.param)
2474 }
2475 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) {
2476 c.ctxt.Diag("literal operation on R0\n%v", p)
2477 }
2478 a := OP_ADDI
2479 if o.a1 == C_UCON {
2480 if d&0xffff != 0 {
2481 log.Fatalf("invalid handling of %v", p)
2482 }
2483 // For UCON operands the value is right shifted 16, using ADDIS if the
2484 // value should be signed, ORIS if unsigned.
2485 v >>= 16
2486 if r == REGZERO && isuint32(uint64(d)) {
2487 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v))
2488 break
2489 }
2490
2491 a = OP_ADDIS
2492 } else if int64(int16(d)) != d {
2493 // Operand is 16 bit value with sign bit set
2494 if o.a1 == C_ANDCON {
2495 // Needs unsigned 16 bit so use ORI
2496 if r == 0 || r == REGZERO {
2497 o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
2498 break
2499 }
2500 // With ADDCON, needs signed 16 bit value, fall through to use ADDI
2501 } else if o.a1 != C_ADDCON {
2502 log.Fatalf("invalid handling of %v", p)
2503 }
2504 }
2505
2506 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v))
2507
2508 case 4: /* add/mul $scon,[r1],r2 */
2509 v := c.regoff(&p.From)
2510
2511 r := int(p.Reg)
2512 if r == 0 {
2513 r = int(p.To.Reg)
2514 }
2515 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 {
2516 c.ctxt.Diag("literal operation on R0\n%v", p)
2517 }
2518 if int32(int16(v)) != v {
2519 log.Fatalf("mishandled instruction %v", p)
2520 }
2521 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2522
2523 case 5: /* syscall */
2524 o1 = c.oprrr(p.As)
2525
2526 case 6: /* logical op Rb,[Rs,]Ra; no literal */
2527 r := int(p.Reg)
2528
2529 if r == 0 {
2530 r = int(p.To.Reg)
2531 }
2532 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM.
2533 switch p.As {
2534 case AROTL:
2535 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
2536 case AROTLW:
2537 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
2538 default:
2539 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2540 }
2541
2542 case 7: /* mov r, soreg ==> stw o(r) */
2543 r := int(p.To.Reg)
2544
2545 if r == 0 {
2546 r = int(o.param)
2547 }
2548 v := c.regoff(&p.To)
2549 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 {
2550 if v != 0 {
2551 c.ctxt.Diag("illegal indexed instruction\n%v", p)
2552 }
2553 if c.ctxt.Flag_shared && r == REG_R13 {
2554 rel := obj.Addrel(c.cursym)
2555 rel.Off = int32(c.pc)
2556 rel.Siz = 4
2557 // This (and the matching part in the load case
2558 // below) are the only places in the ppc64 toolchain
2559 // that knows the name of the tls variable. Possibly
2560 // we could add some assembly syntax so that the name
2561 // of the variable does not have to be assumed.
2562 rel.Sym = c.ctxt.Lookup("runtime.tls_g")
2563 rel.Type = objabi.R_POWER_TLS
2564 }
2565 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
2566 } else {
2567 if int32(int16(v)) != v {
2568 log.Fatalf("mishandled instruction %v", p)
2569 }
2570 // Offsets in DS form stores must be a multiple of 4
2571 inst := c.opstore(p.As)
2572 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2573 log.Fatalf("invalid offset for DS form load/store %v", p)
2574 }
2575 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
2576 }
2577
2578 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */
2579 r := int(p.From.Reg)
2580
2581 if r == 0 {
2582 r = int(o.param)
2583 }
2584 v := c.regoff(&p.From)
2585 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 {
2586 if v != 0 {
2587 c.ctxt.Diag("illegal indexed instruction\n%v", p)
2588 }
2589 if c.ctxt.Flag_shared && r == REG_R13 {
2590 rel := obj.Addrel(c.cursym)
2591 rel.Off = int32(c.pc)
2592 rel.Siz = 4
2593 rel.Sym = c.ctxt.Lookup("runtime.tls_g")
2594 rel.Type = objabi.R_POWER_TLS
2595 }
2596 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
2597 } else {
2598 if int32(int16(v)) != v {
2599 log.Fatalf("mishandled instruction %v", p)
2600 }
2601 // Offsets in DS form loads must be a multiple of 4
2602 inst := c.opload(p.As)
2603 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2604 log.Fatalf("invalid offset for DS form load/store %v", p)
2605 }
2606 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
2607 }
2608
2609 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */
2610 r := int(p.From.Reg)
2611
2612 if r == 0 {
2613 r = int(o.param)
2614 }
2615 v := c.regoff(&p.From)
2616 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 {
2617 if v != 0 {
2618 c.ctxt.Diag("illegal indexed instruction\n%v", p)
2619 }
2620 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
2621 } else {
2622 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2623 }
2624 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
2625
2626 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */
2627 r := int(p.Reg)
2628
2629 if r == 0 {
2630 r = int(p.To.Reg)
2631 }
2632 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
2633
2634 case 11: /* br/bl lbra */
2635 v := int32(0)
2636
2637 if p.To.Target() != nil {
2638 v = int32(p.To.Target().Pc - p.Pc)
2639 if v&03 != 0 {
2640 c.ctxt.Diag("odd branch target address\n%v", p)
2641 v &^= 03
2642 }
2643
2644 if v < -(1<<25) || v >= 1<<24 {
2645 c.ctxt.Diag("branch too far\n%v", p)
2646 }
2647 }
2648
2649 o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
2650 if p.To.Sym != nil {
2651 rel := obj.Addrel(c.cursym)
2652 rel.Off = int32(c.pc)
2653 rel.Siz = 4
2654 rel.Sym = p.To.Sym
2655 v += int32(p.To.Offset)
2656 if v&03 != 0 {
2657 c.ctxt.Diag("odd branch target address\n%v", p)
2658 v &^= 03
2659 }
2660
2661 rel.Add = int64(v)
2662 rel.Type = objabi.R_CALLPOWER
2663 }
2664 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking
2665
2666 case 12: /* movb r,r (extsb); movw r,r (extsw) */
2667 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST {
2668 v := c.regoff(&p.From)
2669 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 {
2670 c.ctxt.Diag("literal operation on R0\n%v", p)
2671 }
2672
2673 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v))
2674 break
2675 }
2676
2677 if p.As == AMOVW {
2678 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2679 } else {
2680 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2681 }
2682
2683 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */
2684 if p.As == AMOVBZ {
2685 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
2686 } else if p.As == AMOVH {
2687 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2688 } else if p.As == AMOVHZ {
2689 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
2690 } else if p.As == AMOVWZ {
2691 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */
2692 } else {
2693 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p)
2694 }
2695
2696 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */
2697 r := int(p.Reg)
2698
2699 if r == 0 {
2700 r = int(p.To.Reg)
2701 }
2702 d := c.vregoff(p.GetFrom3())
2703 var a int
2704 switch p.As {
2705
2706 // These opcodes expect a mask operand that has to be converted into the
2707 // appropriate operand. The way these were defined, not all valid masks are possible.
2708 // Left here for compatibility in case they were used or generated.
2709 case ARLDCL, ARLDCLCC:
2710 var mask [2]uint8
2711 c.maskgen64(p, mask[:], uint64(d))
2712
2713 a = int(mask[0]) /* MB */
2714 if mask[1] != 63 {
2715 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
2716 }
2717 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2718 o1 |= (uint32(a) & 31) << 6
2719 if a&0x20 != 0 {
2720 o1 |= 1 << 5 /* mb[5] is top bit */
2721 }
2722
2723 case ARLDCR, ARLDCRCC:
2724 var mask [2]uint8
2725 c.maskgen64(p, mask[:], uint64(d))
2726
2727 a = int(mask[1]) /* ME */
2728 if mask[0] != 0 {
2729 c.ctxt.Diag("invalid mask for rotate: %x %x (start != 0)\n%v", uint64(d), mask[0], p)
2730 }
2731 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2732 o1 |= (uint32(a) & 31) << 6
2733 if a&0x20 != 0 {
2734 o1 |= 1 << 5 /* mb[5] is top bit */
2735 }
2736
2737 // These opcodes use a shift count like the ppc64 asm, no mask conversion done
2738 case ARLDICR, ARLDICRCC:
2739 me := int(d)
2740 sh := c.regoff(&p.From)
2741 if me < 0 || me > 63 || sh > 63 {
2742 c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh)
2743 }
2744 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me))
2745
2746 case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
2747 mb := int(d)
2748 sh := c.regoff(&p.From)
2749 if mb < 0 || mb > 63 || sh > 63 {
2750 c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh)
2751 }
2752 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb))
2753
2754 case ACLRLSLDI:
2755 // This is an extended mnemonic defined in the ISA section C.8.1
2756 // clrlsldi ra,rs,n,b --> rldic ra,rs,n,b-n
2757 // It maps onto RLDIC so is directly generated here based on the operands from
2758 // the clrlsldi.
2759 b := int(d)
2760 n := c.regoff(&p.From)
2761 if n > int32(b) || b > 63 {
2762 c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b)
2763 }
2764 o1 = AOP_RLDIC(OP_RLDIC, uint32(p.To.Reg), uint32(r), uint32(n), uint32(b)-uint32(n))
2765
2766 default:
2767 c.ctxt.Diag("unexpected op in rldc case\n%v", p)
2768 a = 0
2769 }
2770
2771 case 17, /* bc bo,bi,lbra (same for now) */
2772 16: /* bc bo,bi,sbra */
2773 a := 0
2774
2775 r := int(p.Reg)
2776
2777 if p.From.Type == obj.TYPE_CONST {
2778 a = int(c.regoff(&p.From))
2779 } else if p.From.Type == obj.TYPE_REG {
2780 if r != 0 {
2781 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
2782 }
2783 // BI values for the CR
2784 switch p.From.Reg {
2785 case REG_CR0:
2786 r = BI_CR0
2787 case REG_CR1:
2788 r = BI_CR1
2789 case REG_CR2:
2790 r = BI_CR2
2791 case REG_CR3:
2792 r = BI_CR3
2793 case REG_CR4:
2794 r = BI_CR4
2795 case REG_CR5:
2796 r = BI_CR5
2797 case REG_CR6:
2798 r = BI_CR6
2799 case REG_CR7:
2800 r = BI_CR7
2801 default:
2802 c.ctxt.Diag("unrecognized register: expecting CR\n")
2803 }
2804 }
2805 v := int32(0)
2806 if p.To.Target() != nil {
2807 v = int32(p.To.Target().Pc - p.Pc)
2808 }
2809 if v&03 != 0 {
2810 c.ctxt.Diag("odd branch target address\n%v", p)
2811 v &^= 03
2812 }
2813
2814 if v < -(1<<16) || v >= 1<<15 {
2815 c.ctxt.Diag("branch too far\n%v", p)
2816 }
2817 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
2818
2819 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */
2820 var v int32
2821 if p.As == ABC || p.As == ABCL {
2822 v = c.regoff(&p.To) & 31
2823 } else {
2824 v = 20 /* unconditional */
2825 }
2826 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11
2827 o2 = OPVCC(19, 16, 0, 0)
2828 if p.As == ABL || p.As == ABCL {
2829 o2 |= 1
2830 }
2831 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index))
2832
2833 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */
2834 var v int32
2835 if p.As == ABC || p.As == ABCL {
2836 v = c.regoff(&p.From) & 31
2837 } else {
2838 v = 20 /* unconditional */
2839 }
2840 r := int(p.Reg)
2841 if r == 0 {
2842 r = 0
2843 }
2844 switch oclass(&p.To) {
2845 case C_CTR:
2846 o1 = OPVCC(19, 528, 0, 0)
2847
2848 case C_LR:
2849 o1 = OPVCC(19, 16, 0, 0)
2850
2851 default:
2852 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
2853 v = 0
2854 }
2855
2856 if p.As == ABL || p.As == ABCL {
2857 o1 |= 1
2858 }
2859 o1 = OP_BCR(o1, uint32(v), uint32(r))
2860
2861 case 19: /* mov $lcon,r ==> cau+or */
2862 d := c.vregoff(&p.From)
2863
2864 if p.From.Sym == nil {
2865 o1 = loadu32(int(p.To.Reg), d)
2866 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
2867 } else {
2868 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI)
2869 }
2870
2871 case 20: /* add $ucon,,r | addis $addcon,r,r */
2872 v := c.regoff(&p.From)
2873
2874 r := int(p.Reg)
2875 if r == 0 {
2876 r = int(p.To.Reg)
2877 }
2878 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) {
2879 c.ctxt.Diag("literal operation on R0\n%v", p)
2880 }
2881 if p.As == AADDIS {
2882 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2883 } else {
2884 o1 = AOP_IRR(c.opirr(AADDIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
2885 }
2886
2887 case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add */
2888 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2889 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2890 }
2891 d := c.vregoff(&p.From)
2892 r := int(p.Reg)
2893 if r == 0 {
2894 r = int(p.To.Reg)
2895 }
2896 if p.From.Sym != nil {
2897 c.ctxt.Diag("%v is not supported", p)
2898 }
2899 // If operand is ANDCON, generate 2 instructions using
2900 // ORI for unsigned value; with LCON 3 instructions.
2901 if o.size == 8 {
2902 o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))
2903 o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2904 } else {
2905 o1 = loadu32(REGTMP, d)
2906 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d)))
2907 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2908 }
2909
2910 case 23: /* and $lcon/$addcon,r1,r2 ==> oris+ori+and/addi+and */
2911 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2912 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2913 }
2914 d := c.vregoff(&p.From)
2915 r := int(p.Reg)
2916 if r == 0 {
2917 r = int(p.To.Reg)
2918 }
2919
2920 // With ADDCON operand, generate 2 instructions using ADDI for signed value,
2921 // with LCON operand generate 3 instructions.
2922 if o.size == 8 {
2923 o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
2924 o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2925 } else {
2926 o1 = loadu32(REGTMP, d)
2927 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d)))
2928 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2929 }
2930 if p.From.Sym != nil {
2931 c.ctxt.Diag("%v is not supported", p)
2932 }
2933
2934 case 24: /* lfd fA,float64(0) -> xxlxor xsA,xsaA,xsaA + fneg for -0 */
2935 o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
2936 // This is needed for -0.
2937 if o.size == 8 {
2938 o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
2939 }
2940
2941 case 25:
2942 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */
2943 v := c.regoff(&p.From)
2944
2945 if v < 0 {
2946 v = 0
2947 } else if v > 63 {
2948 v = 63
2949 }
2950 r := int(p.Reg)
2951 if r == 0 {
2952 r = int(p.To.Reg)
2953 }
2954 var a int
2955 op := uint32(0)
2956 switch p.As {
2957 case ASLD, ASLDCC:
2958 a = int(63 - v)
2959 op = OP_RLDICR
2960
2961 case ASRD, ASRDCC:
2962 a = int(v)
2963 v = 64 - v
2964 op = OP_RLDICL
2965 case AROTL:
2966 a = int(0)
2967 op = OP_RLDICL
2968 default:
2969 c.ctxt.Diag("unexpected op in sldi case\n%v", p)
2970 a = 0
2971 o1 = 0
2972 }
2973
2974 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
2975 if p.As == ASLDCC || p.As == ASRDCC {
2976 o1 |= 1 // Set the condition code bit
2977 }
2978
2979 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */
2980 if p.To.Reg == REGTMP {
2981 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2982 }
2983 v := c.regoff(&p.From)
2984 r := int(p.From.Reg)
2985 if r == 0 {
2986 r = int(o.param)
2987 }
2988 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
2989 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v))
2990
2991 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */
2992 v := c.regoff(p.GetFrom3())
2993
2994 r := int(p.From.Reg)
2995 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2996
2997 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */
2998 if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
2999 c.ctxt.Diag("can't synthesize large constant\n%v", p)
3000 }
3001 v := c.regoff(p.GetFrom3())
3002 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
3003 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v))
3004 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
3005 if p.From.Sym != nil {
3006 c.ctxt.Diag("%v is not supported", p)
3007 }
3008
3009 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */
3010 v := c.regoff(&p.From)
3011
3012 d := c.vregoff(p.GetFrom3())
3013 var mask [2]uint8
3014 c.maskgen64(p, mask[:], uint64(d))
3015 var a int
3016 switch p.As {
3017 case ARLDC, ARLDCCC:
3018 a = int(mask[0]) /* MB */
3019 if int32(mask[1]) != (63 - v) {
3020 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), mask[1], v, p)
3021 }
3022
3023 case ARLDCL, ARLDCLCC:
3024 a = int(mask[0]) /* MB */
3025 if mask[1] != 63 {
3026 c.ctxt.Diag("invalid mask for shift: %x %s (shift %d)\n%v", uint64(d), mask[1], v, p)
3027 }
3028
3029 case ARLDCR, ARLDCRCC:
3030 a = int(mask[1]) /* ME */
3031 if mask[0] != 0 {
3032 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), mask[0], v, p)
3033 }
3034
3035 default:
3036 c.ctxt.Diag("unexpected op in rldic case\n%v", p)
3037 a = 0
3038 }
3039
3040 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
3041 o1 |= (uint32(a) & 31) << 6
3042 if v&0x20 != 0 {
3043 o1 |= 1 << 1
3044 }
3045 if a&0x20 != 0 {
3046 o1 |= 1 << 5 /* mb[5] is top bit */
3047 }
3048
3049 case 30: /* rldimi $sh,s,$mask,a */
3050 v := c.regoff(&p.From)
3051
3052 d := c.vregoff(p.GetFrom3())
3053
3054 // Original opcodes had mask operands which had to be converted to a shift count as expected by
3055 // the ppc64 asm.
3056 switch p.As {
3057 case ARLDMI, ARLDMICC:
3058 var mask [2]uint8
3059 c.maskgen64(p, mask[:], uint64(d))
3060 if int32(mask[1]) != (63 - v) {
3061 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), mask[1], v, p)
3062 }
3063 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
3064 o1 |= (uint32(mask[0]) & 31) << 6
3065 if v&0x20 != 0 {
3066 o1 |= 1 << 1
3067 }
3068 if mask[0]&0x20 != 0 {
3069 o1 |= 1 << 5 /* mb[5] is top bit */
3070 }
3071
3072 // Opcodes with shift count operands.
3073 case ARLDIMI, ARLDIMICC:
3074 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
3075 o1 |= (uint32(d) & 31) << 6
3076 if d&0x20 != 0 {
3077 o1 |= 1 << 5
3078 }
3079 if v&0x20 != 0 {
3080 o1 |= 1 << 1
3081 }
3082 }
3083
3084 case 31: /* dword */
3085 d := c.vregoff(&p.From)
3086
3087 if c.ctxt.Arch.ByteOrder == binary.BigEndian {
3088 o1 = uint32(d >> 32)
3089 o2 = uint32(d)
3090 } else {
3091 o1 = uint32(d)
3092 o2 = uint32(d >> 32)
3093 }
3094
3095 if p.From.Sym != nil {
3096 rel := obj.Addrel(c.cursym)
3097 rel.Off = int32(c.pc)
3098 rel.Siz = 8
3099 rel.Sym = p.From.Sym
3100 rel.Add = p.From.Offset
3101 rel.Type = objabi.R_ADDR
3102 o2 = 0
3103 o1 = o2
3104 }
3105
3106 case 32: /* fmul frc,fra,frd */
3107 r := int(p.Reg)
3108
3109 if r == 0 {
3110 r = int(p.To.Reg)
3111 }
3112 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
3113
3114 case 33: /* fabs [frb,]frd; fmr. frb,frd */
3115 r := int(p.From.Reg)
3116
3117 if oclass(&p.From) == C_NONE {
3118 r = int(p.To.Reg)
3119 }
3120 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
3121
3122 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */
3123 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
3124
3125 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */
3126 v := c.regoff(&p.To)
3127
3128 r := int(p.To.Reg)
3129 if r == 0 {
3130 r = int(o.param)
3131 }
3132 // Offsets in DS form stores must be a multiple of 4
3133 inst := c.opstore(p.As)
3134 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3135 log.Fatalf("invalid offset for DS form load/store %v", p)
3136 }
3137 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
3138 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
3139
3140 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */
3141 v := c.regoff(&p.From)
3142
3143 r := int(p.From.Reg)
3144 if r == 0 {
3145 r = int(o.param)
3146 }
3147 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
3148 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v))
3149
3150 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */
3151 v := c.regoff(&p.From)
3152
3153 r := int(p.From.Reg)
3154 if r == 0 {
3155 r = int(o.param)
3156 }
3157 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
3158 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v))
3159 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3160
3161 case 40: /* word */
3162 o1 = uint32(c.regoff(&p.From))
3163
3164 case 41: /* stswi */
3165 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3166
3167 case 42: /* lswi */
3168 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3169
3170 case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */
3171 /* TH field for dcbt/dcbtst: */
3172 /* 0 = Block access - program will soon access EA. */
3173 /* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */
3174 /* 16 = Block access - program will soon make a transient access to EA. */
3175 /* 17 = Block access - program will not access EA for a long time. */
3176
3177 /* L field for dcbf: */
3178 /* 0 = invalidates the block containing EA in all processors. */
3179 /* 1 = same as 0, but with limited scope (i.e. block in the current processor will not be reused soon). */
3180 /* 3 = same as 1, but with even more limited scope (i.e. block in the current processor primary cache will not be reused soon). */
3181 if p.To.Type == obj.TYPE_NONE {
3182 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
3183 } else {
3184 th := c.regoff(&p.To)
3185 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
3186 }
3187
3188 case 44: /* indexed store */
3189 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3190
3191 case 45: /* indexed load */
3192 switch p.As {
3193 /* The assembler accepts a 4-operand l*arx instruction. The fourth operand is an Exclusive Access Hint (EH) */
3194 /* The EH field can be used as a lock acquire/release hint as follows: */
3195 /* 0 = Atomic Update (fetch-and-operate or similar algorithm) */
3196 /* 1 = Exclusive Access (lock acquire and release) */
3197 case ALBAR, ALHAR, ALWAR, ALDAR:
3198 if p.From3Type() != obj.TYPE_NONE {
3199 eh := int(c.regoff(p.GetFrom3()))
3200 if eh > 1 {
3201 c.ctxt.Diag("illegal EH field\n%v", p)
3202 }
3203 o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
3204 } else {
3205 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3206 }
3207 default:
3208 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3209 }
3210 case 46: /* plain op */
3211 o1 = c.oprrr(p.As)
3212
3213 case 47: /* op Ra, Rd; also op [Ra,] Rd */
3214 r := int(p.From.Reg)
3215
3216 if r == 0 {
3217 r = int(p.To.Reg)
3218 }
3219 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3220
3221 case 48: /* op Rs, Ra */
3222 r := int(p.From.Reg)
3223
3224 if r == 0 {
3225 r = int(p.To.Reg)
3226 }
3227 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3228
3229 case 49: /* op Rb; op $n, Rb */
3230 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */
3231 v := c.regoff(&p.From) & 1
3232 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
3233 } else {
3234 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
3235 }
3236
3237 case 50: /* rem[u] r1[,r2],r3 */
3238 r := int(p.Reg)
3239
3240 if r == 0 {
3241 r = int(p.To.Reg)
3242 }
3243 v := c.oprrr(p.As)
3244 t := v & (1<<10 | 1) /* OE|Rc */
3245 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3246 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
3247 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3248 if p.As == AREMU {
3249 o4 = o3
3250
3251 /* Clear top 32 bits */
3252 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
3253 }
3254
3255 case 51: /* remd[u] r1[,r2],r3 */
3256 r := int(p.Reg)
3257
3258 if r == 0 {
3259 r = int(p.To.Reg)
3260 }
3261 v := c.oprrr(p.As)
3262 t := v & (1<<10 | 1) /* OE|Rc */
3263 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3264 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
3265 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3266 /* cases 50,51: removed; can be reused. */
3267
3268 /* cases 50,51: removed; can be reused. */
3269
3270 case 52: /* mtfsbNx cr(n) */
3271 v := c.regoff(&p.From) & 31
3272
3273 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
3274
3275 case 53: /* mffsX ,fr1 */
3276 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
3277
3278 case 54: /* mov msr,r1; mov r1, msr*/
3279 if oclass(&p.From) == C_REG {
3280 if p.As == AMOVD {
3281 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0)
3282 } else {
3283 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0)
3284 }
3285 } else {
3286 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0)
3287 }
3288
3289 case 55: /* op Rb, Rd */
3290 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
3291
3292 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */
3293 v := c.regoff(&p.From)
3294
3295 r := int(p.Reg)
3296 if r == 0 {
3297 r = int(p.To.Reg)
3298 }
3299 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
3300 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
3301 o1 |= 1 << 1 /* mb[5] */
3302 }
3303
3304 case 57: /* slw $sh,[s,]a -> rlwinm ... */
3305 v := c.regoff(&p.From)
3306
3307 r := int(p.Reg)
3308 if r == 0 {
3309 r = int(p.To.Reg)
3310 }
3311
3312 /*
3313 * Let user (gs) shoot himself in the foot.
3314 * qc has already complained.
3315 *
3316 if(v < 0 || v > 31)
3317 ctxt->diag("illegal shift %ld\n%v", v, p);
3318 */
3319 if v < 0 {
3320 v = 0
3321 } else if v > 32 {
3322 v = 32
3323 }
3324 var mask [2]uint8
3325 switch p.As {
3326 case AROTLW:
3327 mask[0], mask[1] = 0, 31
3328 case ASRW, ASRWCC:
3329 mask[0], mask[1] = uint8(v), 31
3330 v = 32 - v
3331 default:
3332 mask[0], mask[1] = 0, uint8(31-v)
3333 }
3334 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
3335 if p.As == ASLWCC || p.As == ASRWCC {
3336 o1 |= 1 // set the condition code
3337 }
3338
3339 case 58: /* logical $andcon,[s],a */
3340 v := c.regoff(&p.From)
3341
3342 r := int(p.Reg)
3343 if r == 0 {
3344 r = int(p.To.Reg)
3345 }
3346 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3347
3348 case 59: /* or/xor/and $ucon,,r | oris/xoris/andis $addcon,r,r */
3349 v := c.regoff(&p.From)
3350
3351 r := int(p.Reg)
3352 if r == 0 {
3353 r = int(p.To.Reg)
3354 }
3355 switch p.As {
3356 case AOR:
3357 o1 = LOP_IRR(c.opirr(AORIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis. */
3358 case AXOR:
3359 o1 = LOP_IRR(c.opirr(AXORIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
3360 case AANDCC:
3361 o1 = LOP_IRR(c.opirr(AANDISCC), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
3362 default:
3363 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3364 }
3365
3366 case 60: /* tw to,a,b */
3367 r := int(c.regoff(&p.From) & 31)
3368
3369 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
3370
3371 case 61: /* tw to,a,$simm */
3372 r := int(c.regoff(&p.From) & 31)
3373
3374 v := c.regoff(&p.To)
3375 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
3376
3377 case 62: /* rlwmi $sh,s,$mask,a */
3378 v := c.regoff(&p.From)
3379 switch p.As {
3380 case ACLRLSLWI:
3381 b := c.regoff(p.GetFrom3())
3382 // This is an extended mnemonic described in the ISA C.8.2
3383 // clrlslwi ra,rs,n,b -> rlwinm ra,rs,n,b-n,31-n
3384 // It maps onto rlwinm which is directly generated here.
3385 if v < 0 || v > 32 || b > 32 {
3386 c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, b)
3387 }
3388 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(v), uint32(b-v), uint32(31-v))
3389 default:
3390 var mask [2]uint8
3391 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
3392 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v))
3393 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
3394 }
3395
3396 case 63: /* rlwmi b,s,$mask,a */
3397 v := c.regoff(&p.From)
3398 switch p.As {
3399 case ACLRLSLWI:
3400 b := c.regoff(p.GetFrom3())
3401 if v > b || b > 32 {
3402 // Message will match operands from the ISA even though in the
3403 // code it uses 'v'
3404 c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, b)
3405 }
3406 // This is an extended mnemonic described in the ISA C.8.2
3407 // clrlslwi ra,rs,n,b -> rlwinm ra,rs,n,b-n,31-n
3408 // It generates the rlwinm directly here.
3409 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(v), uint32(b-v), uint32(31-v))
3410 default:
3411 var mask [2]uint8
3412 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
3413 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v))
3414 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
3415 }
3416
3417 case 64: /* mtfsf fr[, $m] {,fpcsr} */
3418 var v int32
3419 if p.From3Type() != obj.TYPE_NONE {
3420 v = c.regoff(p.GetFrom3()) & 255
3421 } else {
3422 v = 255
3423 }
3424 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
3425
3426 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */
3427 if p.To.Reg == 0 {
3428 c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
3429 }
3430 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
3431
3432 case 66: /* mov spr,r1; mov r1,spr, also dcr */
3433 var r int
3434 var v int32
3435 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
3436 r = int(p.From.Reg)
3437 v = int32(p.To.Reg)
3438 if REG_DCR0 <= v && v <= REG_DCR0+1023 {
3439 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */
3440 } else {
3441 o1 = OPVCC(31, 467, 0, 0) /* mtspr */
3442 }
3443 } else {
3444 r = int(p.To.Reg)
3445 v = int32(p.From.Reg)
3446 if REG_DCR0 <= v && v <= REG_DCR0+1023 {
3447 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */
3448 } else {
3449 o1 = OPVCC(31, 339, 0, 0) /* mfspr */
3450 }
3451 }
3452
3453 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3454
3455 case 67: /* mcrf crfD,crfS */
3456 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
3457 c.ctxt.Diag("illegal CR field number\n%v", p)
3458 }
3459 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
3460
3461 case 68: /* mfcr rD; mfocrf CRM,rD */
3462 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 {
3463 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */
3464 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */
3465 } else {
3466 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */
3467 }
3468
3469 case 69: /* mtcrf CRM,rS */
3470 var v int32
3471 if p.From3Type() != obj.TYPE_NONE {
3472 if p.To.Reg != 0 {
3473 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p)
3474 }
3475 v = c.regoff(p.GetFrom3()) & 0xff
3476 } else {
3477 if p.To.Reg == 0 {
3478 v = 0xff /* CR */
3479 } else {
3480 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */
3481 }
3482 }
3483
3484 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12
3485
3486 case 70: /* [f]cmp r,r,cr*/
3487 var r int
3488 if p.Reg == 0 {
3489 r = 0
3490 } else {
3491 r = (int(p.Reg) & 7) << 2
3492 }
3493 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg))
3494
3495 case 71: /* cmp[l] r,i,cr*/
3496 var r int
3497 if p.Reg == 0 {
3498 r = 0
3499 } else {
3500 r = (int(p.Reg) & 7) << 2
3501 }
3502 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff
3503
3504 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */
3505 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
3506
3507 case 73: /* mcrfs crfD,crfS */
3508 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
3509 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
3510 }
3511 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
3512
3513 case 77: /* syscall $scon, syscall Rx */
3514 if p.From.Type == obj.TYPE_CONST {
3515 if p.From.Offset > BIG || p.From.Offset < -BIG {
3516 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
3517 }
3518 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
3519 } else if p.From.Type == obj.TYPE_REG {
3520 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
3521 } else {
3522 c.ctxt.Diag("illegal syscall: %v", p)
3523 o1 = 0x7fe00008 // trap always
3524 }
3525
3526 o2 = c.oprrr(p.As)
3527 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0
3528
3529 case 78: /* undef */
3530 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed
3531 always to be an illegal instruction." */
3532
3533 /* relocation operations */
3534 case 74:
3535 v := c.vregoff(&p.To)
3536 // Offsets in DS form stores must be a multiple of 4
3537 inst := c.opstore(p.As)
3538 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3539 log.Fatalf("invalid offset for DS form load/store %v", p)
3540 }
3541 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst)
3542
3543 //if(dlm) reloc(&p->to, p->pc, 1);
3544
3545 case 75:
3546 v := c.vregoff(&p.From)
3547 // Offsets in DS form loads must be a multiple of 4
3548 inst := c.opload(p.As)
3549 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3550 log.Fatalf("invalid offset for DS form load/store %v", p)
3551 }
3552 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst)
3553
3554 //if(dlm) reloc(&p->from, p->pc, 1);
3555
3556 case 76:
3557 v := c.vregoff(&p.From)
3558 // Offsets in DS form loads must be a multiple of 4
3559 inst := c.opload(p.As)
3560 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3561 log.Fatalf("invalid offset for DS form load/store %v", p)
3562 }
3563 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst)
3564 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3565
3566 //if(dlm) reloc(&p->from, p->pc, 1);
3567
3568 case 79:
3569 if p.From.Offset != 0 {
3570 c.ctxt.Diag("invalid offset against tls var %v", p)
3571 }
3572 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0)
3573 rel := obj.Addrel(c.cursym)
3574 rel.Off = int32(c.pc)
3575 rel.Siz = 4
3576 rel.Sym = p.From.Sym
3577 rel.Type = objabi.R_POWER_TLS_LE
3578
3579 case 80:
3580 if p.From.Offset != 0 {
3581 c.ctxt.Diag("invalid offset against tls var %v", p)
3582 }
3583 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3584 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
3585 rel := obj.Addrel(c.cursym)
3586 rel.Off = int32(c.pc)
3587 rel.Siz = 8
3588 rel.Sym = p.From.Sym
3589 rel.Type = objabi.R_POWER_TLS_IE
3590
3591 case 81:
3592 v := c.vregoff(&p.To)
3593 if v != 0 {
3594 c.ctxt.Diag("invalid offset against GOT slot %v", p)
3595 }
3596
3597 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3598 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
3599 rel := obj.Addrel(c.cursym)
3600 rel.Off = int32(c.pc)
3601 rel.Siz = 8
3602 rel.Sym = p.From.Sym
3603 rel.Type = objabi.R_ADDRPOWER_GOT
3604 case 82: /* vector instructions, VX-form and VC-form */
3605 if p.From.Type == obj.TYPE_REG {
3606 /* reg reg none OR reg reg reg */
3607 /* 3-register operand order: VRA, VRB, VRT */
3608 /* 2-register operand order: VRA, VRT */
3609 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3610 } else if p.From3Type() == obj.TYPE_CONST {
3611 /* imm imm reg reg */
3612 /* operand order: SIX, VRA, ST, VRT */
3613 six := int(c.regoff(&p.From))
3614 st := int(c.regoff(p.GetFrom3()))
3615 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
3616 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
3617 /* imm reg reg */
3618 /* operand order: UIM, VRB, VRT */
3619 uim := int(c.regoff(&p.From))
3620 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
3621 } else {
3622 /* imm reg */
3623 /* operand order: SIM, VRT */
3624 sim := int(c.regoff(&p.From))
3625 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
3626 }
3627
3628 case 83: /* vector instructions, VA-form */
3629 if p.From.Type == obj.TYPE_REG {
3630 /* reg reg reg reg */
3631 /* 4-register operand order: VRA, VRB, VRC, VRT */
3632 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3633 } else if p.From.Type == obj.TYPE_CONST {
3634 /* imm reg reg reg */
3635 /* operand order: SHB, VRA, VRB, VRT */
3636 shb := int(c.regoff(&p.From))
3637 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
3638 }
3639
3640 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc
3641 bc := c.vregoff(&p.From)
3642
3643 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg
3644 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
3645
3646 case 85: /* vector instructions, VX-form */
3647 /* reg none reg */
3648 /* 2-register operand order: VRB, VRT */
3649 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
3650
3651 case 86: /* VSX indexed store, XX1-form */
3652 /* reg reg reg */
3653 /* 3-register operand order: XT, (RB)(RA*1) */
3654 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3655
3656 case 87: /* VSX indexed load, XX1-form */
3657 /* reg reg reg */
3658 /* 3-register operand order: (RB)(RA*1), XT */
3659 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3660
3661 case 88: /* VSX instructions, XX1-form */
3662 /* reg reg none OR reg reg reg */
3663 /* 3-register operand order: RA, RB, XT */
3664 /* 2-register operand order: XS, RA or RA, XT */
3665 xt := int32(p.To.Reg)
3666 xs := int32(p.From.Reg)
3667 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */
3668 if REG_V0 <= xt && xt <= REG_V31 {
3669 /* Convert V0-V31 to VS32-VS63 */
3670 xt = xt + 64
3671 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
3672 } else if REG_F0 <= xt && xt <= REG_F31 {
3673 /* Convert F0-F31 to VS0-VS31 */
3674 xt = xt + 64
3675 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
3676 } else if REG_VS0 <= xt && xt <= REG_VS63 {
3677 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
3678 } else if REG_V0 <= xs && xs <= REG_V31 {
3679 /* Likewise for XS */
3680 xs = xs + 64
3681 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
3682 } else if REG_F0 <= xs && xs <= REG_F31 {
3683 xs = xs + 64
3684 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
3685 } else if REG_VS0 <= xs && xs <= REG_VS63 {
3686 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
3687 }
3688
3689 case 89: /* VSX instructions, XX2-form */
3690 /* reg none reg OR reg imm reg */
3691 /* 2-register operand order: XB, XT or XB, UIM, XT*/
3692 uim := int(c.regoff(p.GetFrom3()))
3693 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
3694
3695 case 90: /* VSX instructions, XX3-form */
3696 if p.From3Type() == obj.TYPE_NONE {
3697 /* reg reg reg */
3698 /* 3-register operand order: XA, XB, XT */
3699 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3700 } else if p.From3Type() == obj.TYPE_CONST {
3701 /* reg reg reg imm */
3702 /* operand order: XA, XB, DM, XT */
3703 dm := int(c.regoff(p.GetFrom3()))
3704 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
3705 }
3706
3707 case 91: /* VSX instructions, XX4-form */
3708 /* reg reg reg reg */
3709 /* 3-register operand order: XA, XB, XC, XT */
3710 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3711
3712 case 92: /* X-form instructions, 3-operands */
3713 if p.To.Type == obj.TYPE_CONST {
3714 /* imm reg reg */
3715 xf := int32(p.From.Reg)
3716 if REG_F0 <= xf && xf <= REG_F31 {
3717 /* operand order: FRA, FRB, BF */
3718 bf := int(c.regoff(&p.To)) << 2
3719 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3720 } else {
3721 /* operand order: RA, RB, L */
3722 l := int(c.regoff(&p.To))
3723 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
3724 }
3725 } else if p.From3Type() == obj.TYPE_CONST {
3726 /* reg reg imm */
3727 /* operand order: RB, L, RA */
3728 l := int(c.regoff(p.GetFrom3()))
3729 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
3730 } else if p.To.Type == obj.TYPE_REG {
3731 cr := int32(p.To.Reg)
3732 if REG_CR0 <= cr && cr <= REG_CR7 {
3733 /* cr reg reg */
3734 /* operand order: RA, RB, BF */
3735 bf := (int(p.To.Reg) & 7) << 2
3736 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3737 } else if p.From.Type == obj.TYPE_CONST {
3738 /* reg imm */
3739 /* operand order: L, RT */
3740 l := int(c.regoff(&p.From))
3741 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
3742 } else {
3743 switch p.As {
3744 case ACOPY, APASTECC:
3745 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
3746 default:
3747 /* reg reg reg */
3748 /* operand order: RS, RB, RA */
3749 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3750 }
3751 }
3752 }
3753
3754 case 93: /* X-form instructions, 2-operands */
3755 if p.To.Type == obj.TYPE_CONST {
3756 /* imm reg */
3757 /* operand order: FRB, BF */
3758 bf := int(c.regoff(&p.To)) << 2
3759 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
3760 } else if p.Reg == 0 {
3761 /* popcnt* r,r, X-form */
3762 /* operand order: RS, RA */
3763 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3764 }
3765
3766 case 94: /* Z23-form instructions, 4-operands */
3767 /* reg reg reg imm */
3768 /* operand order: RA, RB, CY, RT */
3769 cy := int(c.regoff(p.GetFrom3()))
3770 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
3771
3772 case 95: /* Retrieve TOC relative symbol */
3773 /* This code is for AIX only */
3774 v := c.vregoff(&p.From)
3775 if v != 0 {
3776 c.ctxt.Diag("invalid offset against TOC slot %v", p)
3777 }
3778
3779 inst := c.opload(p.As)
3780 if c.opform(inst) != DS_FORM {
3781 c.ctxt.Diag("invalid form for a TOC access in %v", p)
3782 }
3783
3784 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3785 o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3786 rel := obj.Addrel(c.cursym)
3787 rel.Off = int32(c.pc)
3788 rel.Siz = 8
3789 rel.Sym = p.From.Sym
3790 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
3791
3792 case 96: /* VSX load, DQ-form */
3793 /* reg imm reg */
3794 /* operand order: (RA)(DQ), XT */
3795 dq := int16(c.regoff(&p.From))
3796 if (dq & 15) != 0 {
3797 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3798 }
3799 o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq))
3800
3801 case 97: /* VSX store, DQ-form */
3802 /* reg imm reg */
3803 /* operand order: XT, (RA)(DQ) */
3804 dq := int16(c.regoff(&p.To))
3805 if (dq & 15) != 0 {
3806 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3807 }
3808 o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq))
3809 case 98: /* VSX indexed load or load with length (also left-justified), x-form */
3810 /* vsreg, reg, reg */
3811 o1 = AOP_XX1(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3812 case 99: /* VSX store with length (also left-justified) x-form */
3813 /* reg, reg, vsreg */
3814 o1 = AOP_XX1(c.opstore(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
3815 case 100: /* VSX X-form XXSPLTIB */
3816 if p.From.Type == obj.TYPE_CONST {
3817 /* imm reg */
3818 uim := int(c.regoff(&p.From))
3819 /* imm reg */
3820 /* Use AOP_XX1 form with 0 for one of the registers. */
3821 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(uim))
3822 } else {
3823 c.ctxt.Diag("invalid ops for %v", p.As)
3824 }
3825 case 101:
3826 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg))
3827 }
3828
3829 out[0] = o1
3830 out[1] = o2
3831 out[2] = o3
3832 out[3] = o4
3833 out[4] = o5
3834 }
3835
3836 func (c *ctxt9) vregoff(a *obj.Addr) int64 {
3837 c.instoffset = 0
3838 if a != nil {
3839 c.aclass(a)
3840 }
3841 return c.instoffset
3842 }
3843
3844 func (c *ctxt9) regoff(a *obj.Addr) int32 {
3845 return int32(c.vregoff(a))
3846 }
3847
3848 func (c *ctxt9) oprrr(a obj.As) uint32 {
3849 switch a {
3850 case AADD:
3851 return OPVCC(31, 266, 0, 0)
3852 case AADDCC:
3853 return OPVCC(31, 266, 0, 1)
3854 case AADDV:
3855 return OPVCC(31, 266, 1, 0)
3856 case AADDVCC:
3857 return OPVCC(31, 266, 1, 1)
3858 case AADDC:
3859 return OPVCC(31, 10, 0, 0)
3860 case AADDCCC:
3861 return OPVCC(31, 10, 0, 1)
3862 case AADDCV:
3863 return OPVCC(31, 10, 1, 0)
3864 case AADDCVCC:
3865 return OPVCC(31, 10, 1, 1)
3866 case AADDE:
3867 return OPVCC(31, 138, 0, 0)
3868 case AADDECC:
3869 return OPVCC(31, 138, 0, 1)
3870 case AADDEV:
3871 return OPVCC(31, 138, 1, 0)
3872 case AADDEVCC:
3873 return OPVCC(31, 138, 1, 1)
3874 case AADDME:
3875 return OPVCC(31, 234, 0, 0)
3876 case AADDMECC:
3877 return OPVCC(31, 234, 0, 1)
3878 case AADDMEV:
3879 return OPVCC(31, 234, 1, 0)
3880 case AADDMEVCC:
3881 return OPVCC(31, 234, 1, 1)
3882 case AADDZE:
3883 return OPVCC(31, 202, 0, 0)
3884 case AADDZECC:
3885 return OPVCC(31, 202, 0, 1)
3886 case AADDZEV:
3887 return OPVCC(31, 202, 1, 0)
3888 case AADDZEVCC:
3889 return OPVCC(31, 202, 1, 1)
3890 case AADDEX:
3891 return OPVCC(31, 170, 0, 0) /* addex - v3.0b */
3892
3893 case AAND:
3894 return OPVCC(31, 28, 0, 0)
3895 case AANDCC:
3896 return OPVCC(31, 28, 0, 1)
3897 case AANDN:
3898 return OPVCC(31, 60, 0, 0)
3899 case AANDNCC:
3900 return OPVCC(31, 60, 0, 1)
3901
3902 case ACMP:
3903 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */
3904 case ACMPU:
3905 return OPVCC(31, 32, 0, 0) | 1<<21
3906 case ACMPW:
3907 return OPVCC(31, 0, 0, 0) /* L=0 */
3908 case ACMPWU:
3909 return OPVCC(31, 32, 0, 0)
3910 case ACMPB:
3911 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */
3912 case ACMPEQB:
3913 return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */
3914
3915 case ACNTLZW:
3916 return OPVCC(31, 26, 0, 0)
3917 case ACNTLZWCC:
3918 return OPVCC(31, 26, 0, 1)
3919 case ACNTLZD:
3920 return OPVCC(31, 58, 0, 0)
3921 case ACNTLZDCC:
3922 return OPVCC(31, 58, 0, 1)
3923
3924 case ACRAND:
3925 return OPVCC(19, 257, 0, 0)
3926 case ACRANDN:
3927 return OPVCC(19, 129, 0, 0)
3928 case ACREQV:
3929 return OPVCC(19, 289, 0, 0)
3930 case ACRNAND:
3931 return OPVCC(19, 225, 0, 0)
3932 case ACRNOR:
3933 return OPVCC(19, 33, 0, 0)
3934 case ACROR:
3935 return OPVCC(19, 449, 0, 0)
3936 case ACRORN:
3937 return OPVCC(19, 417, 0, 0)
3938 case ACRXOR:
3939 return OPVCC(19, 193, 0, 0)
3940
3941 case ADCBF:
3942 return OPVCC(31, 86, 0, 0)
3943 case ADCBI:
3944 return OPVCC(31, 470, 0, 0)
3945 case ADCBST:
3946 return OPVCC(31, 54, 0, 0)
3947 case ADCBT:
3948 return OPVCC(31, 278, 0, 0)
3949 case ADCBTST:
3950 return OPVCC(31, 246, 0, 0)
3951 case ADCBZ:
3952 return OPVCC(31, 1014, 0, 0)
3953
3954 case AMODUD:
3955 return OPVCC(31, 265, 0, 0) /* modud - v3.0 */
3956 case AMODUW:
3957 return OPVCC(31, 267, 0, 0) /* moduw - v3.0 */
3958 case AMODSD:
3959 return OPVCC(31, 777, 0, 0) /* modsd - v3.0 */
3960 case AMODSW:
3961 return OPVCC(31, 779, 0, 0) /* modsw - v3.0 */
3962
3963 case ADIVW, AREM:
3964 return OPVCC(31, 491, 0, 0)
3965
3966 case ADIVWCC:
3967 return OPVCC(31, 491, 0, 1)
3968
3969 case ADIVWV:
3970 return OPVCC(31, 491, 1, 0)
3971
3972 case ADIVWVCC:
3973 return OPVCC(31, 491, 1, 1)
3974
3975 case ADIVWU, AREMU:
3976 return OPVCC(31, 459, 0, 0)
3977
3978 case ADIVWUCC:
3979 return OPVCC(31, 459, 0, 1)
3980
3981 case ADIVWUV:
3982 return OPVCC(31, 459, 1, 0)
3983
3984 case ADIVWUVCC:
3985 return OPVCC(31, 459, 1, 1)
3986
3987 case ADIVD, AREMD:
3988 return OPVCC(31, 489, 0, 0)
3989
3990 case ADIVDCC:
3991 return OPVCC(31, 489, 0, 1)
3992
3993 case ADIVDE:
3994 return OPVCC(31, 425, 0, 0)
3995
3996 case ADIVDECC:
3997 return OPVCC(31, 425, 0, 1)
3998
3999 case ADIVDEU:
4000 return OPVCC(31, 393, 0, 0)
4001
4002 case ADIVDEUCC:
4003 return OPVCC(31, 393, 0, 1)
4004
4005 case ADIVDV:
4006 return OPVCC(31, 489, 1, 0)
4007
4008 case ADIVDVCC:
4009 return OPVCC(31, 489, 1, 1)
4010
4011 case ADIVDU, AREMDU:
4012 return OPVCC(31, 457, 0, 0)
4013
4014 case ADIVDUCC:
4015 return OPVCC(31, 457, 0, 1)
4016
4017 case ADIVDUV:
4018 return OPVCC(31, 457, 1, 0)
4019
4020 case ADIVDUVCC:
4021 return OPVCC(31, 457, 1, 1)
4022
4023 case AEIEIO:
4024 return OPVCC(31, 854, 0, 0)
4025
4026 case AEQV:
4027 return OPVCC(31, 284, 0, 0)
4028 case AEQVCC:
4029 return OPVCC(31, 284, 0, 1)
4030
4031 case AEXTSB:
4032 return OPVCC(31, 954, 0, 0)
4033 case AEXTSBCC:
4034 return OPVCC(31, 954, 0, 1)
4035 case AEXTSH:
4036 return OPVCC(31, 922, 0, 0)
4037 case AEXTSHCC:
4038 return OPVCC(31, 922, 0, 1)
4039 case AEXTSW:
4040 return OPVCC(31, 986, 0, 0)
4041 case AEXTSWCC:
4042 return OPVCC(31, 986, 0, 1)
4043
4044 case AFABS:
4045 return OPVCC(63, 264, 0, 0)
4046 case AFABSCC:
4047 return OPVCC(63, 264, 0, 1)
4048 case AFADD:
4049 return OPVCC(63, 21, 0, 0)
4050 case AFADDCC:
4051 return OPVCC(63, 21, 0, 1)
4052 case AFADDS:
4053 return OPVCC(59, 21, 0, 0)
4054 case AFADDSCC:
4055 return OPVCC(59, 21, 0, 1)
4056 case AFCMPO:
4057 return OPVCC(63, 32, 0, 0)
4058 case AFCMPU:
4059 return OPVCC(63, 0, 0, 0)
4060 case AFCFID:
4061 return OPVCC(63, 846, 0, 0)
4062 case AFCFIDCC:
4063 return OPVCC(63, 846, 0, 1)
4064 case AFCFIDU:
4065 return OPVCC(63, 974, 0, 0)
4066 case AFCFIDUCC:
4067 return OPVCC(63, 974, 0, 1)
4068 case AFCFIDS:
4069 return OPVCC(59, 846, 0, 0)
4070 case AFCFIDSCC:
4071 return OPVCC(59, 846, 0, 1)
4072 case AFCTIW:
4073 return OPVCC(63, 14, 0, 0)
4074 case AFCTIWCC:
4075 return OPVCC(63, 14, 0, 1)
4076 case AFCTIWZ:
4077 return OPVCC(63, 15, 0, 0)
4078 case AFCTIWZCC:
4079 return OPVCC(63, 15, 0, 1)
4080 case AFCTID:
4081 return OPVCC(63, 814, 0, 0)
4082 case AFCTIDCC:
4083 return OPVCC(63, 814, 0, 1)
4084 case AFCTIDZ:
4085 return OPVCC(63, 815, 0, 0)
4086 case AFCTIDZCC:
4087 return OPVCC(63, 815, 0, 1)
4088 case AFDIV:
4089 return OPVCC(63, 18, 0, 0)
4090 case AFDIVCC:
4091 return OPVCC(63, 18, 0, 1)
4092 case AFDIVS:
4093 return OPVCC(59, 18, 0, 0)
4094 case AFDIVSCC:
4095 return OPVCC(59, 18, 0, 1)
4096 case AFMADD:
4097 return OPVCC(63, 29, 0, 0)
4098 case AFMADDCC:
4099 return OPVCC(63, 29, 0, 1)
4100 case AFMADDS:
4101 return OPVCC(59, 29, 0, 0)
4102 case AFMADDSCC:
4103 return OPVCC(59, 29, 0, 1)
4104
4105 case AFMOVS, AFMOVD:
4106 return OPVCC(63, 72, 0, 0) /* load */
4107 case AFMOVDCC:
4108 return OPVCC(63, 72, 0, 1)
4109 case AFMSUB:
4110 return OPVCC(63, 28, 0, 0)
4111 case AFMSUBCC:
4112 return OPVCC(63, 28, 0, 1)
4113 case AFMSUBS:
4114 return OPVCC(59, 28, 0, 0)
4115 case AFMSUBSCC:
4116 return OPVCC(59, 28, 0, 1)
4117 case AFMUL:
4118 return OPVCC(63, 25, 0, 0)
4119 case AFMULCC:
4120 return OPVCC(63, 25, 0, 1)
4121 case AFMULS:
4122 return OPVCC(59, 25, 0, 0)
4123 case AFMULSCC:
4124 return OPVCC(59, 25, 0, 1)
4125 case AFNABS:
4126 return OPVCC(63, 136, 0, 0)
4127 case AFNABSCC:
4128 return OPVCC(63, 136, 0, 1)
4129 case AFNEG:
4130 return OPVCC(63, 40, 0, 0)
4131 case AFNEGCC:
4132 return OPVCC(63, 40, 0, 1)
4133 case AFNMADD:
4134 return OPVCC(63, 31, 0, 0)
4135 case AFNMADDCC:
4136 return OPVCC(63, 31, 0, 1)
4137 case AFNMADDS:
4138 return OPVCC(59, 31, 0, 0)
4139 case AFNMADDSCC:
4140 return OPVCC(59, 31, 0, 1)
4141 case AFNMSUB:
4142 return OPVCC(63, 30, 0, 0)
4143 case AFNMSUBCC:
4144 return OPVCC(63, 30, 0, 1)
4145 case AFNMSUBS:
4146 return OPVCC(59, 30, 0, 0)
4147 case AFNMSUBSCC:
4148 return OPVCC(59, 30, 0, 1)
4149 case AFCPSGN:
4150 return OPVCC(63, 8, 0, 0)
4151 case AFCPSGNCC:
4152 return OPVCC(63, 8, 0, 1)
4153 case AFRES:
4154 return OPVCC(59, 24, 0, 0)
4155 case AFRESCC:
4156 return OPVCC(59, 24, 0, 1)
4157 case AFRIM:
4158 return OPVCC(63, 488, 0, 0)
4159 case AFRIMCC:
4160 return OPVCC(63, 488, 0, 1)
4161 case AFRIP:
4162 return OPVCC(63, 456, 0, 0)
4163 case AFRIPCC:
4164 return OPVCC(63, 456, 0, 1)
4165 case AFRIZ:
4166 return OPVCC(63, 424, 0, 0)
4167 case AFRIZCC:
4168 return OPVCC(63, 424, 0, 1)
4169 case AFRIN:
4170 return OPVCC(63, 392, 0, 0)
4171 case AFRINCC:
4172 return OPVCC(63, 392, 0, 1)
4173 case AFRSP:
4174 return OPVCC(63, 12, 0, 0)
4175 case AFRSPCC:
4176 return OPVCC(63, 12, 0, 1)
4177 case AFRSQRTE:
4178 return OPVCC(63, 26, 0, 0)
4179 case AFRSQRTECC:
4180 return OPVCC(63, 26, 0, 1)
4181 case AFSEL:
4182 return OPVCC(63, 23, 0, 0)
4183 case AFSELCC:
4184 return OPVCC(63, 23, 0, 1)
4185 case AFSQRT:
4186 return OPVCC(63, 22, 0, 0)
4187 case AFSQRTCC:
4188 return OPVCC(63, 22, 0, 1)
4189 case AFSQRTS:
4190 return OPVCC(59, 22, 0, 0)
4191 case AFSQRTSCC:
4192 return OPVCC(59, 22, 0, 1)
4193 case AFSUB:
4194 return OPVCC(63, 20, 0, 0)
4195 case AFSUBCC:
4196 return OPVCC(63, 20, 0, 1)
4197 case AFSUBS:
4198 return OPVCC(59, 20, 0, 0)
4199 case AFSUBSCC:
4200 return OPVCC(59, 20, 0, 1)
4201
4202 case AICBI:
4203 return OPVCC(31, 982, 0, 0)
4204 case AISYNC:
4205 return OPVCC(19, 150, 0, 0)
4206
4207 case AMTFSB0:
4208 return OPVCC(63, 70, 0, 0)
4209 case AMTFSB0CC:
4210 return OPVCC(63, 70, 0, 1)
4211 case AMTFSB1:
4212 return OPVCC(63, 38, 0, 0)
4213 case AMTFSB1CC:
4214 return OPVCC(63, 38, 0, 1)
4215
4216 case AMULHW:
4217 return OPVCC(31, 75, 0, 0)
4218 case AMULHWCC:
4219 return OPVCC(31, 75, 0, 1)
4220 case AMULHWU:
4221 return OPVCC(31, 11, 0, 0)
4222 case AMULHWUCC:
4223 return OPVCC(31, 11, 0, 1)
4224 case AMULLW:
4225 return OPVCC(31, 235, 0, 0)
4226 case AMULLWCC:
4227 return OPVCC(31, 235, 0, 1)
4228 case AMULLWV:
4229 return OPVCC(31, 235, 1, 0)
4230 case AMULLWVCC:
4231 return OPVCC(31, 235, 1, 1)
4232
4233 case AMULHD:
4234 return OPVCC(31, 73, 0, 0)
4235 case AMULHDCC:
4236 return OPVCC(31, 73, 0, 1)
4237 case AMULHDU:
4238 return OPVCC(31, 9, 0, 0)
4239 case AMULHDUCC:
4240 return OPVCC(31, 9, 0, 1)
4241 case AMULLD:
4242 return OPVCC(31, 233, 0, 0)
4243 case AMULLDCC:
4244 return OPVCC(31, 233, 0, 1)
4245 case AMULLDV:
4246 return OPVCC(31, 233, 1, 0)
4247 case AMULLDVCC:
4248 return OPVCC(31, 233, 1, 1)
4249
4250 case ANAND:
4251 return OPVCC(31, 476, 0, 0)
4252 case ANANDCC:
4253 return OPVCC(31, 476, 0, 1)
4254 case ANEG:
4255 return OPVCC(31, 104, 0, 0)
4256 case ANEGCC:
4257 return OPVCC(31, 104, 0, 1)
4258 case ANEGV:
4259 return OPVCC(31, 104, 1, 0)
4260 case ANEGVCC:
4261 return OPVCC(31, 104, 1, 1)
4262 case ANOR:
4263 return OPVCC(31, 124, 0, 0)
4264 case ANORCC:
4265 return OPVCC(31, 124, 0, 1)
4266 case AOR:
4267 return OPVCC(31, 444, 0, 0)
4268 case AORCC:
4269 return OPVCC(31, 444, 0, 1)
4270 case AORN:
4271 return OPVCC(31, 412, 0, 0)
4272 case AORNCC:
4273 return OPVCC(31, 412, 0, 1)
4274
4275 case APOPCNTD:
4276 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */
4277 case APOPCNTW:
4278 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */
4279 case APOPCNTB:
4280 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */
4281 case ACNTTZW:
4282 return OPVCC(31, 538, 0, 0) /* cnttzw - v3.00 */
4283 case ACNTTZWCC:
4284 return OPVCC(31, 538, 0, 1) /* cnttzw. - v3.00 */
4285 case ACNTTZD:
4286 return OPVCC(31, 570, 0, 0) /* cnttzd - v3.00 */
4287 case ACNTTZDCC:
4288 return OPVCC(31, 570, 0, 1) /* cnttzd. - v3.00 */
4289
4290 case ARFI:
4291 return OPVCC(19, 50, 0, 0)
4292 case ARFCI:
4293 return OPVCC(19, 51, 0, 0)
4294 case ARFID:
4295 return OPVCC(19, 18, 0, 0)
4296 case AHRFID:
4297 return OPVCC(19, 274, 0, 0)
4298
4299 case ARLWMI:
4300 return OPVCC(20, 0, 0, 0)
4301 case ARLWMICC:
4302 return OPVCC(20, 0, 0, 1)
4303 case ARLWNM:
4304 return OPVCC(23, 0, 0, 0)
4305 case ARLWNMCC:
4306 return OPVCC(23, 0, 0, 1)
4307
4308 case ARLDCL:
4309 return OPVCC(30, 8, 0, 0)
4310 case ARLDCLCC:
4311 return OPVCC(30, 0, 0, 1)
4312
4313 case ARLDCR:
4314 return OPVCC(30, 9, 0, 0)
4315 case ARLDCRCC:
4316 return OPVCC(30, 9, 0, 1)
4317
4318 case ARLDICL:
4319 return OPVCC(30, 0, 0, 0)
4320 case ARLDICLCC:
4321 return OPVCC(30, 0, 0, 1)
4322 case ARLDICR:
4323 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr
4324 case ARLDICRCC:
4325 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr.
4326
4327 case ARLDIC:
4328 return OPVCC(30, 0, 0, 0) | 4<<1 // rldic
4329 case ARLDICCC:
4330 return OPVCC(30, 0, 0, 1) | 4<<1 // rldic.
4331
4332 case ASYSCALL:
4333 return OPVCC(17, 1, 0, 0)
4334
4335 case ASLW:
4336 return OPVCC(31, 24, 0, 0)
4337 case ASLWCC:
4338 return OPVCC(31, 24, 0, 1)
4339 case ASLD:
4340 return OPVCC(31, 27, 0, 0)
4341 case ASLDCC:
4342 return OPVCC(31, 27, 0, 1)
4343
4344 case ASRAW:
4345 return OPVCC(31, 792, 0, 0)
4346 case ASRAWCC:
4347 return OPVCC(31, 792, 0, 1)
4348 case ASRAD:
4349 return OPVCC(31, 794, 0, 0)
4350 case ASRADCC:
4351 return OPVCC(31, 794, 0, 1)
4352
4353 case ASRW:
4354 return OPVCC(31, 536, 0, 0)
4355 case ASRWCC:
4356 return OPVCC(31, 536, 0, 1)
4357 case ASRD:
4358 return OPVCC(31, 539, 0, 0)
4359 case ASRDCC:
4360 return OPVCC(31, 539, 0, 1)
4361
4362 case ASUB:
4363 return OPVCC(31, 40, 0, 0)
4364 case ASUBCC:
4365 return OPVCC(31, 40, 0, 1)
4366 case ASUBV:
4367 return OPVCC(31, 40, 1, 0)
4368 case ASUBVCC:
4369 return OPVCC(31, 40, 1, 1)
4370 case ASUBC:
4371 return OPVCC(31, 8, 0, 0)
4372 case ASUBCCC:
4373 return OPVCC(31, 8, 0, 1)
4374 case ASUBCV:
4375 return OPVCC(31, 8, 1, 0)
4376 case ASUBCVCC:
4377 return OPVCC(31, 8, 1, 1)
4378 case ASUBE:
4379 return OPVCC(31, 136, 0, 0)
4380 case ASUBECC:
4381 return OPVCC(31, 136, 0, 1)
4382 case ASUBEV:
4383 return OPVCC(31, 136, 1, 0)
4384 case ASUBEVCC:
4385 return OPVCC(31, 136, 1, 1)
4386 case ASUBME:
4387 return OPVCC(31, 232, 0, 0)
4388 case ASUBMECC:
4389 return OPVCC(31, 232, 0, 1)
4390 case ASUBMEV:
4391 return OPVCC(31, 232, 1, 0)
4392 case ASUBMEVCC:
4393 return OPVCC(31, 232, 1, 1)
4394 case ASUBZE:
4395 return OPVCC(31, 200, 0, 0)
4396 case ASUBZECC:
4397 return OPVCC(31, 200, 0, 1)
4398 case ASUBZEV:
4399 return OPVCC(31, 200, 1, 0)
4400 case ASUBZEVCC:
4401 return OPVCC(31, 200, 1, 1)
4402
4403 case ASYNC:
4404 return OPVCC(31, 598, 0, 0)
4405 case ALWSYNC:
4406 return OPVCC(31, 598, 0, 0) | 1<<21
4407
4408 case APTESYNC:
4409 return OPVCC(31, 598, 0, 0) | 2<<21
4410
4411 case ATLBIE:
4412 return OPVCC(31, 306, 0, 0)
4413 case ATLBIEL:
4414 return OPVCC(31, 274, 0, 0)
4415 case ATLBSYNC:
4416 return OPVCC(31, 566, 0, 0)
4417 case ASLBIA:
4418 return OPVCC(31, 498, 0, 0)
4419 case ASLBIE:
4420 return OPVCC(31, 434, 0, 0)
4421 case ASLBMFEE:
4422 return OPVCC(31, 915, 0, 0)
4423 case ASLBMFEV:
4424 return OPVCC(31, 851, 0, 0)
4425 case ASLBMTE:
4426 return OPVCC(31, 402, 0, 0)
4427
4428 case ATW:
4429 return OPVCC(31, 4, 0, 0)
4430 case ATD:
4431 return OPVCC(31, 68, 0, 0)
4432
4433 /* Vector (VMX/Altivec) instructions */
4434 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */
4435 /* are enabled starting at POWER6 (ISA 2.05). */
4436 case AVAND:
4437 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */
4438 case AVANDC:
4439 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */
4440 case AVNAND:
4441 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */
4442
4443 case AVOR:
4444 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */
4445 case AVORC:
4446 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */
4447 case AVNOR:
4448 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */
4449 case AVXOR:
4450 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */
4451 case AVEQV:
4452 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */
4453
4454 case AVADDUBM:
4455 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */
4456 case AVADDUHM:
4457 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */
4458 case AVADDUWM:
4459 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */
4460 case AVADDUDM:
4461 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */
4462 case AVADDUQM:
4463 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */
4464
4465 case AVADDCUQ:
4466 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */
4467 case AVADDCUW:
4468 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */
4469
4470 case AVADDUBS:
4471 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */
4472 case AVADDUHS:
4473 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */
4474 case AVADDUWS:
4475 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */
4476
4477 case AVADDSBS:
4478 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */
4479 case AVADDSHS:
4480 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */
4481 case AVADDSWS:
4482 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */
4483
4484 case AVADDEUQM:
4485 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */
4486 case AVADDECUQ:
4487 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */
4488
4489 case AVMULESB:
4490 return OPVX(4, 776, 0, 0) /* vmulesb - v2.03 */
4491 case AVMULOSB:
4492 return OPVX(4, 264, 0, 0) /* vmulosb - v2.03 */
4493 case AVMULEUB:
4494 return OPVX(4, 520, 0, 0) /* vmuleub - v2.03 */
4495 case AVMULOUB:
4496 return OPVX(4, 8, 0, 0) /* vmuloub - v2.03 */
4497 case AVMULESH:
4498 return OPVX(4, 840, 0, 0) /* vmulesh - v2.03 */
4499 case AVMULOSH:
4500 return OPVX(4, 328, 0, 0) /* vmulosh - v2.03 */
4501 case AVMULEUH:
4502 return OPVX(4, 584, 0, 0) /* vmuleuh - v2.03 */
4503 case AVMULOUH:
4504 return OPVX(4, 72, 0, 0) /* vmulouh - v2.03 */
4505 case AVMULESW:
4506 return OPVX(4, 904, 0, 0) /* vmulesw - v2.07 */
4507 case AVMULOSW:
4508 return OPVX(4, 392, 0, 0) /* vmulosw - v2.07 */
4509 case AVMULEUW:
4510 return OPVX(4, 648, 0, 0) /* vmuleuw - v2.07 */
4511 case AVMULOUW:
4512 return OPVX(4, 136, 0, 0) /* vmulouw - v2.07 */
4513 case AVMULUWM:
4514 return OPVX(4, 137, 0, 0) /* vmuluwm - v2.07 */
4515
4516 case AVPMSUMB:
4517 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */
4518 case AVPMSUMH:
4519 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */
4520 case AVPMSUMW:
4521 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */
4522 case AVPMSUMD:
4523 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */
4524
4525 case AVMSUMUDM:
4526 return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */
4527
4528 case AVSUBUBM:
4529 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */
4530 case AVSUBUHM:
4531 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */
4532 case AVSUBUWM:
4533 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */
4534 case AVSUBUDM:
4535 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */
4536 case AVSUBUQM:
4537 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */
4538
4539 case AVSUBCUQ:
4540 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */
4541 case AVSUBCUW:
4542 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */
4543
4544 case AVSUBUBS:
4545 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */
4546 case AVSUBUHS:
4547 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */
4548 case AVSUBUWS:
4549 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */
4550
4551 case AVSUBSBS:
4552 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */
4553 case AVSUBSHS:
4554 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */
4555 case AVSUBSWS:
4556 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */
4557
4558 case AVSUBEUQM:
4559 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */
4560 case AVSUBECUQ:
4561 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */
4562
4563 case AVRLB:
4564 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */
4565 case AVRLH:
4566 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */
4567 case AVRLW:
4568 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */
4569 case AVRLD:
4570 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */
4571
4572 case AVMRGOW:
4573 return OPVX(4, 1676, 0, 0) /* vmrgow - v2.07 */
4574 case AVMRGEW:
4575 return OPVX(4, 1932, 0, 0) /* vmrgew - v2.07 */
4576
4577 case AVSLB:
4578 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */
4579 case AVSLH:
4580 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */
4581 case AVSLW:
4582 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */
4583 case AVSL:
4584 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */
4585 case AVSLO:
4586 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */
4587 case AVSRB:
4588 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */
4589 case AVSRH:
4590 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */
4591 case AVSRW:
4592 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */
4593 case AVSR:
4594 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */
4595 case AVSRO:
4596 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */
4597 case AVSLD:
4598 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */
4599 case AVSRD:
4600 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */
4601
4602 case AVSRAB:
4603 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */
4604 case AVSRAH:
4605 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */
4606 case AVSRAW:
4607 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */
4608 case AVSRAD:
4609 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */
4610
4611 case AVBPERMQ:
4612 return OPVC(4, 1356, 0, 0) /* vbpermq - v2.07 */
4613 case AVBPERMD:
4614 return OPVC(4, 1484, 0, 0) /* vbpermd - v3.00 */
4615
4616 case AVCLZB:
4617 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */
4618 case AVCLZH:
4619 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */
4620 case AVCLZW:
4621 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */
4622 case AVCLZD:
4623 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */
4624
4625 case AVPOPCNTB:
4626 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */
4627 case AVPOPCNTH:
4628 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */
4629 case AVPOPCNTW:
4630 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */
4631 case AVPOPCNTD:
4632 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */
4633
4634 case AVCMPEQUB:
4635 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */
4636 case AVCMPEQUBCC:
4637 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */
4638 case AVCMPEQUH:
4639 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */
4640 case AVCMPEQUHCC:
4641 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */
4642 case AVCMPEQUW:
4643 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */
4644 case AVCMPEQUWCC:
4645 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */
4646 case AVCMPEQUD:
4647 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */
4648 case AVCMPEQUDCC:
4649 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */
4650
4651 case AVCMPGTUB:
4652 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */
4653 case AVCMPGTUBCC:
4654 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */
4655 case AVCMPGTUH:
4656 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */
4657 case AVCMPGTUHCC:
4658 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */
4659 case AVCMPGTUW:
4660 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */
4661 case AVCMPGTUWCC:
4662 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */
4663 case AVCMPGTUD:
4664 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */
4665 case AVCMPGTUDCC:
4666 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */
4667 case AVCMPGTSB:
4668 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */
4669 case AVCMPGTSBCC:
4670 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */
4671 case AVCMPGTSH:
4672 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */
4673 case AVCMPGTSHCC:
4674 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */
4675 case AVCMPGTSW:
4676 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */
4677 case AVCMPGTSWCC:
4678 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */
4679 case AVCMPGTSD:
4680 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */
4681 case AVCMPGTSDCC:
4682 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */
4683
4684 case AVCMPNEZB:
4685 return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */
4686 case AVCMPNEZBCC:
4687 return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */
4688 case AVCMPNEB:
4689 return OPVC(4, 7, 0, 0) /* vcmpneb - v3.00 */
4690 case AVCMPNEBCC:
4691 return OPVC(4, 7, 0, 1) /* vcmpneb. - v3.00 */
4692 case AVCMPNEH:
4693 return OPVC(4, 71, 0, 0) /* vcmpneh - v3.00 */
4694 case AVCMPNEHCC:
4695 return OPVC(4, 71, 0, 1) /* vcmpneh. - v3.00 */
4696 case AVCMPNEW:
4697 return OPVC(4, 135, 0, 0) /* vcmpnew - v3.00 */
4698 case AVCMPNEWCC:
4699 return OPVC(4, 135, 0, 1) /* vcmpnew. - v3.00 */
4700
4701 case AVPERM:
4702 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */
4703 case AVPERMXOR:
4704 return OPVX(4, 45, 0, 0) /* vpermxor - v2.03 */
4705 case AVPERMR:
4706 return OPVX(4, 59, 0, 0) /* vpermr - v3.0 */
4707
4708 case AVSEL:
4709 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */
4710
4711 case AVCIPHER:
4712 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */
4713 case AVCIPHERLAST:
4714 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */
4715 case AVNCIPHER:
4716 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */
4717 case AVNCIPHERLAST:
4718 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */
4719 case AVSBOX:
4720 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */
4721 /* End of vector instructions */
4722
4723 /* Vector scalar (VSX) instructions */
4724 /* ISA 2.06 enables these for POWER7. */
4725 case AMFVSRD, AMFVRD, AMFFPRD:
4726 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */
4727 case AMFVSRWZ:
4728 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */
4729 case AMFVSRLD:
4730 return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */
4731
4732 case AMTVSRD, AMTFPRD, AMTVRD:
4733 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */
4734 case AMTVSRWA:
4735 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */
4736 case AMTVSRWZ:
4737 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */
4738 case AMTVSRDD:
4739 return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */
4740 case AMTVSRWS:
4741 return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */
4742
4743 case AXXLAND:
4744 return OPVXX3(60, 130, 0) /* xxland - v2.06 */
4745 case AXXLANDC:
4746 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */
4747 case AXXLEQV:
4748 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */
4749 case AXXLNAND:
4750 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */
4751
4752 case AXXLORC:
4753 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */
4754 case AXXLNOR:
4755 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */
4756 case AXXLOR, AXXLORQ:
4757 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */
4758 case AXXLXOR:
4759 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */
4760
4761 case AXXSEL:
4762 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */
4763
4764 case AXXMRGHW:
4765 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */
4766 case AXXMRGLW:
4767 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */
4768
4769 case AXXSPLTW:
4770 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */
4771
4772 case AXXSPLTIB:
4773 return OPVCC(60, 360, 0, 0) /* xxspltib - v3.0 */
4774
4775 case AXXPERM:
4776 return OPVXX3(60, 26, 0) /* xxperm - v2.06 */
4777 case AXXPERMDI:
4778 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */
4779
4780 case AXXSLDWI:
4781 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */
4782
4783 case AXXBRQ:
4784 return OPVXX2VA(60, 475, 31) /* xxbrq - v3.0 */
4785 case AXXBRD:
4786 return OPVXX2VA(60, 475, 23) /* xxbrd - v3.0 */
4787 case AXXBRW:
4788 return OPVXX2VA(60, 475, 15) /* xxbrw - v3.0 */
4789 case AXXBRH:
4790 return OPVXX2VA(60, 475, 7) /* xxbrh - v3.0 */
4791
4792 case AXSCVDPSP:
4793 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */
4794 case AXSCVSPDP:
4795 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */
4796 case AXSCVDPSPN:
4797 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */
4798 case AXSCVSPDPN:
4799 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */
4800
4801 case AXVCVDPSP:
4802 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */
4803 case AXVCVSPDP:
4804 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */
4805
4806 case AXSCVDPSXDS:
4807 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */
4808 case AXSCVDPSXWS:
4809 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */
4810 case AXSCVDPUXDS:
4811 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */
4812 case AXSCVDPUXWS:
4813 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */
4814
4815 case AXSCVSXDDP:
4816 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */
4817 case AXSCVUXDDP:
4818 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */
4819 case AXSCVSXDSP:
4820 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */
4821 case AXSCVUXDSP:
4822 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */
4823
4824 case AXVCVDPSXDS:
4825 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */
4826 case AXVCVDPSXWS:
4827 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */
4828 case AXVCVDPUXDS:
4829 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */
4830 case AXVCVDPUXWS:
4831 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */
4832 case AXVCVSPSXDS:
4833 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */
4834 case AXVCVSPSXWS:
4835 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */
4836 case AXVCVSPUXDS:
4837 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */
4838 case AXVCVSPUXWS:
4839 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */
4840
4841 case AXVCVSXDDP:
4842 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */
4843 case AXVCVSXWDP:
4844 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */
4845 case AXVCVUXDDP:
4846 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */
4847 case AXVCVUXWDP:
4848 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */
4849 case AXVCVSXDSP:
4850 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */
4851 case AXVCVSXWSP:
4852 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */
4853 case AXVCVUXDSP:
4854 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */
4855 case AXVCVUXWSP:
4856 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */
4857 /* End of VSX instructions */
4858
4859 case AMADDHD:
4860 return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */
4861 case AMADDHDU:
4862 return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */
4863 case AMADDLD:
4864 return OPVX(4, 51, 0, 0) /* maddld - v3.00 */
4865
4866 case AXOR:
4867 return OPVCC(31, 316, 0, 0)
4868 case AXORCC:
4869 return OPVCC(31, 316, 0, 1)
4870 }
4871
4872 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
4873 return 0
4874 }
4875
4876 func (c *ctxt9) opirrr(a obj.As) uint32 {
4877 switch a {
4878 /* Vector (VMX/Altivec) instructions */
4879 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */
4880 /* are enabled starting at POWER6 (ISA 2.05). */
4881 case AVSLDOI:
4882 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */
4883 }
4884
4885 c.ctxt.Diag("bad i/r/r/r opcode %v", a)
4886 return 0
4887 }
4888
4889 func (c *ctxt9) opiirr(a obj.As) uint32 {
4890 switch a {
4891 /* Vector (VMX/Altivec) instructions */
4892 /* ISA 2.07 enables these for POWER8 and beyond. */
4893 case AVSHASIGMAW:
4894 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */
4895 case AVSHASIGMAD:
4896 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */
4897 }
4898
4899 c.ctxt.Diag("bad i/i/r/r opcode %v", a)
4900 return 0
4901 }
4902
4903 func (c *ctxt9) opirr(a obj.As) uint32 {
4904 switch a {
4905 case AADD:
4906 return OPVCC(14, 0, 0, 0)
4907 case AADDC:
4908 return OPVCC(12, 0, 0, 0)
4909 case AADDCCC:
4910 return OPVCC(13, 0, 0, 0)
4911 case AADDIS:
4912 return OPVCC(15, 0, 0, 0) /* ADDIS */
4913
4914 case AANDCC:
4915 return OPVCC(28, 0, 0, 0)
4916 case AANDISCC:
4917 return OPVCC(29, 0, 0, 0) /* ANDIS. */
4918
4919 case ABR:
4920 return OPVCC(18, 0, 0, 0)
4921 case ABL:
4922 return OPVCC(18, 0, 0, 0) | 1
4923 case obj.ADUFFZERO:
4924 return OPVCC(18, 0, 0, 0) | 1
4925 case obj.ADUFFCOPY:
4926 return OPVCC(18, 0, 0, 0) | 1
4927 case ABC:
4928 return OPVCC(16, 0, 0, 0)
4929 case ABCL:
4930 return OPVCC(16, 0, 0, 0) | 1
4931
4932 case ABEQ:
4933 return AOP_RRR(16<<26, 12, 2, 0)
4934 case ABGE:
4935 return AOP_RRR(16<<26, 4, 0, 0)
4936 case ABGT:
4937 return AOP_RRR(16<<26, 12, 1, 0)
4938 case ABLE:
4939 return AOP_RRR(16<<26, 4, 1, 0)
4940 case ABLT:
4941 return AOP_RRR(16<<26, 12, 0, 0)
4942 case ABNE:
4943 return AOP_RRR(16<<26, 4, 2, 0)
4944 case ABVC:
4945 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear
4946 case ABVS:
4947 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set
4948
4949 case ACMP:
4950 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */
4951 case ACMPU:
4952 return OPVCC(10, 0, 0, 0) | 1<<21
4953 case ACMPW:
4954 return OPVCC(11, 0, 0, 0) /* L=0 */
4955 case ACMPWU:
4956 return OPVCC(10, 0, 0, 0)
4957 case ACMPEQB:
4958 return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */
4959
4960 case ALSW:
4961 return OPVCC(31, 597, 0, 0)
4962
4963 case ACOPY:
4964 return OPVCC(31, 774, 0, 0) /* copy - v3.00 */
4965 case APASTECC:
4966 return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */
4967 case ADARN:
4968 return OPVCC(31, 755, 0, 0) /* darn - v3.00 */
4969
4970 case AMULLW:
4971 return OPVCC(7, 0, 0, 0)
4972
4973 case AOR:
4974 return OPVCC(24, 0, 0, 0)
4975 case AORIS:
4976 return OPVCC(25, 0, 0, 0) /* ORIS */
4977
4978 case ARLWMI:
4979 return OPVCC(20, 0, 0, 0) /* rlwimi */
4980 case ARLWMICC:
4981 return OPVCC(20, 0, 0, 1)
4982 case ARLDMI:
4983 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */
4984 case ARLDMICC:
4985 return OPVCC(30, 0, 0, 1) | 3<<2
4986 case ARLDIMI:
4987 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */
4988 case ARLDIMICC:
4989 return OPVCC(30, 0, 0, 1) | 3<<2
4990 case ARLWNM:
4991 return OPVCC(21, 0, 0, 0) /* rlwinm */
4992 case ARLWNMCC:
4993 return OPVCC(21, 0, 0, 1)
4994
4995 case ARLDCL:
4996 return OPVCC(30, 0, 0, 0) /* rldicl */
4997 case ARLDCLCC:
4998 return OPVCC(30, 0, 0, 1)
4999 case ARLDCR:
5000 return OPVCC(30, 1, 0, 0) /* rldicr */
5001 case ARLDCRCC:
5002 return OPVCC(30, 1, 0, 1)
5003 case ARLDC:
5004 return OPVCC(30, 0, 0, 0) | 2<<2
5005 case ARLDCCC:
5006 return OPVCC(30, 0, 0, 1) | 2<<2
5007
5008 case ASRAW:
5009 return OPVCC(31, 824, 0, 0)
5010 case ASRAWCC:
5011 return OPVCC(31, 824, 0, 1)
5012 case ASRAD:
5013 return OPVCC(31, (413 << 1), 0, 0)
5014 case ASRADCC:
5015 return OPVCC(31, (413 << 1), 0, 1)
5016
5017 case ASTSW:
5018 return OPVCC(31, 725, 0, 0)
5019
5020 case ASUBC:
5021 return OPVCC(8, 0, 0, 0)
5022
5023 case ATW:
5024 return OPVCC(3, 0, 0, 0)
5025 case ATD:
5026 return OPVCC(2, 0, 0, 0)
5027
5028 /* Vector (VMX/Altivec) instructions */
5029 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */
5030 /* are enabled starting at POWER6 (ISA 2.05). */
5031 case AVSPLTB:
5032 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */
5033 case AVSPLTH:
5034 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */
5035 case AVSPLTW:
5036 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */
5037
5038 case AVSPLTISB:
5039 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */
5040 case AVSPLTISH:
5041 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */
5042 case AVSPLTISW:
5043 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */
5044 /* End of vector instructions */
5045
5046 case AFTDIV:
5047 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */
5048 case AFTSQRT:
5049 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */
5050
5051 case AXOR:
5052 return OPVCC(26, 0, 0, 0) /* XORIL */
5053 case AXORIS:
5054 return OPVCC(27, 0, 0, 0) /* XORIS */
5055 }
5056
5057 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
5058 return 0
5059 }
5060
5061 /*
5062 * load o(a),d
5063 */
5064 func (c *ctxt9) opload(a obj.As) uint32 {
5065 switch a {
5066 case AMOVD:
5067 return OPVCC(58, 0, 0, 0) /* ld */
5068 case AMOVDU:
5069 return OPVCC(58, 0, 0, 1) /* ldu */
5070 case AMOVWZ:
5071 return OPVCC(32, 0, 0, 0) /* lwz */
5072 case AMOVWZU:
5073 return OPVCC(33, 0, 0, 0) /* lwzu */
5074 case AMOVW:
5075 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */
5076 case ALXV:
5077 return OPDQ(61, 1, 0) /* lxv - ISA v3.0 */
5078 case ALXVL:
5079 return OPVXX1(31, 269, 0) /* lxvl - ISA v3.0 */
5080 case ALXVLL:
5081 return OPVXX1(31, 301, 0) /* lxvll - ISA v3.0 */
5082 case ALXVX:
5083 return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
5084
5085 /* no AMOVWU */
5086 case AMOVB, AMOVBZ:
5087 return OPVCC(34, 0, 0, 0)
5088 /* load */
5089
5090 case AMOVBU, AMOVBZU:
5091 return OPVCC(35, 0, 0, 0)
5092 case AFMOVD:
5093 return OPVCC(50, 0, 0, 0)
5094 case AFMOVDU:
5095 return OPVCC(51, 0, 0, 0)
5096 case AFMOVS:
5097 return OPVCC(48, 0, 0, 0)
5098 case AFMOVSU:
5099 return OPVCC(49, 0, 0, 0)
5100 case AMOVH:
5101 return OPVCC(42, 0, 0, 0)
5102 case AMOVHU:
5103 return OPVCC(43, 0, 0, 0)
5104 case AMOVHZ:
5105 return OPVCC(40, 0, 0, 0)
5106 case AMOVHZU:
5107 return OPVCC(41, 0, 0, 0)
5108 case AMOVMW:
5109 return OPVCC(46, 0, 0, 0) /* lmw */
5110 }
5111
5112 c.ctxt.Diag("bad load opcode %v", a)
5113 return 0
5114 }
5115
5116 /*
5117 * indexed load a(b),d
5118 */
5119 func (c *ctxt9) oploadx(a obj.As) uint32 {
5120 switch a {
5121 case AMOVWZ:
5122 return OPVCC(31, 23, 0, 0) /* lwzx */
5123 case AMOVWZU:
5124 return OPVCC(31, 55, 0, 0) /* lwzux */
5125 case AMOVW:
5126 return OPVCC(31, 341, 0, 0) /* lwax */
5127 case AMOVWU:
5128 return OPVCC(31, 373, 0, 0) /* lwaux */
5129
5130 case AMOVB, AMOVBZ:
5131 return OPVCC(31, 87, 0, 0) /* lbzx */
5132
5133 case AMOVBU, AMOVBZU:
5134 return OPVCC(31, 119, 0, 0) /* lbzux */
5135 case AFMOVD:
5136 return OPVCC(31, 599, 0, 0) /* lfdx */
5137 case AFMOVDU:
5138 return OPVCC(31, 631, 0, 0) /* lfdux */
5139 case AFMOVS:
5140 return OPVCC(31, 535, 0, 0) /* lfsx */
5141 case AFMOVSU:
5142 return OPVCC(31, 567, 0, 0) /* lfsux */
5143 case AFMOVSX:
5144 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */
5145 case AFMOVSZ:
5146 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */
5147 case AMOVH:
5148 return OPVCC(31, 343, 0, 0) /* lhax */
5149 case AMOVHU:
5150 return OPVCC(31, 375, 0, 0) /* lhaux */
5151 case AMOVHBR:
5152 return OPVCC(31, 790, 0, 0) /* lhbrx */
5153 case AMOVWBR:
5154 return OPVCC(31, 534, 0, 0) /* lwbrx */
5155 case AMOVDBR:
5156 return OPVCC(31, 532, 0, 0) /* ldbrx */
5157 case AMOVHZ:
5158 return OPVCC(31, 279, 0, 0) /* lhzx */
5159 case AMOVHZU:
5160 return OPVCC(31, 311, 0, 0) /* lhzux */
5161 case AECIWX:
5162 return OPVCC(31, 310, 0, 0) /* eciwx */
5163 case ALBAR:
5164 return OPVCC(31, 52, 0, 0) /* lbarx */
5165 case ALHAR:
5166 return OPVCC(31, 116, 0, 0) /* lharx */
5167 case ALWAR:
5168 return OPVCC(31, 20, 0, 0) /* lwarx */
5169 case ALDAR:
5170 return OPVCC(31, 84, 0, 0) /* ldarx */
5171 case ALSW:
5172 return OPVCC(31, 533, 0, 0) /* lswx */
5173 case AMOVD:
5174 return OPVCC(31, 21, 0, 0) /* ldx */
5175 case AMOVDU:
5176 return OPVCC(31, 53, 0, 0) /* ldux */
5177 case ALDMX:
5178 return OPVCC(31, 309, 0, 0) /* ldmx */
5179
5180 /* Vector (VMX/Altivec) instructions */
5181 case ALVEBX:
5182 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */
5183 case ALVEHX:
5184 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */
5185 case ALVEWX:
5186 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */
5187 case ALVX:
5188 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */
5189 case ALVXL:
5190 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */
5191 case ALVSL:
5192 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */
5193 case ALVSR:
5194 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */
5195 /* End of vector instructions */
5196
5197 /* Vector scalar (VSX) instructions */
5198 case ALXVX:
5199 return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
5200 case ALXVD2X:
5201 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */
5202 case ALXVW4X:
5203 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */
5204 case ALXVH8X:
5205 return OPVXX1(31, 812, 0) /* lxvh8x - v3.00 */
5206 case ALXVB16X:
5207 return OPVXX1(31, 876, 0) /* lxvb16x - v3.00 */
5208 case ALXVDSX:
5209 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */
5210 case ALXSDX:
5211 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */
5212 case ALXSIWAX:
5213 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */
5214 case ALXSIWZX:
5215 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */
5216 }
5217
5218 c.ctxt.Diag("bad loadx opcode %v", a)
5219 return 0
5220 }
5221
5222 /*
5223 * store s,o(d)
5224 */
5225 func (c *ctxt9) opstore(a obj.As) uint32 {
5226 switch a {
5227 case AMOVB, AMOVBZ:
5228 return OPVCC(38, 0, 0, 0) /* stb */
5229
5230 case AMOVBU, AMOVBZU:
5231 return OPVCC(39, 0, 0, 0) /* stbu */
5232 case AFMOVD:
5233 return OPVCC(54, 0, 0, 0) /* stfd */
5234 case AFMOVDU:
5235 return OPVCC(55, 0, 0, 0) /* stfdu */
5236 case AFMOVS:
5237 return OPVCC(52, 0, 0, 0) /* stfs */
5238 case AFMOVSU:
5239 return OPVCC(53, 0, 0, 0) /* stfsu */
5240
5241 case AMOVHZ, AMOVH:
5242 return OPVCC(44, 0, 0, 0) /* sth */
5243
5244 case AMOVHZU, AMOVHU:
5245 return OPVCC(45, 0, 0, 0) /* sthu */
5246 case AMOVMW:
5247 return OPVCC(47, 0, 0, 0) /* stmw */
5248 case ASTSW:
5249 return OPVCC(31, 725, 0, 0) /* stswi */
5250
5251 case AMOVWZ, AMOVW:
5252 return OPVCC(36, 0, 0, 0) /* stw */
5253
5254 case AMOVWZU, AMOVWU:
5255 return OPVCC(37, 0, 0, 0) /* stwu */
5256 case AMOVD:
5257 return OPVCC(62, 0, 0, 0) /* std */
5258 case AMOVDU:
5259 return OPVCC(62, 0, 0, 1) /* stdu */
5260 case ASTXV:
5261 return OPDQ(61, 5, 0) /* stxv ISA 3.0 */
5262 case ASTXVL:
5263 return OPVXX1(31, 397, 0) /* stxvl ISA 3.0 */
5264 case ASTXVLL:
5265 return OPVXX1(31, 429, 0) /* stxvll ISA 3.0 */
5266 case ASTXVX:
5267 return OPVXX1(31, 396, 0) /* stxvx - ISA v3.0 */
5268
5269 }
5270
5271 c.ctxt.Diag("unknown store opcode %v", a)
5272 return 0
5273 }
5274
5275 /*
5276 * indexed store s,a(b)
5277 */
5278 func (c *ctxt9) opstorex(a obj.As) uint32 {
5279 switch a {
5280 case AMOVB, AMOVBZ:
5281 return OPVCC(31, 215, 0, 0) /* stbx */
5282
5283 case AMOVBU, AMOVBZU:
5284 return OPVCC(31, 247, 0, 0) /* stbux */
5285 case AFMOVD:
5286 return OPVCC(31, 727, 0, 0) /* stfdx */
5287 case AFMOVDU:
5288 return OPVCC(31, 759, 0, 0) /* stfdux */
5289 case AFMOVS:
5290 return OPVCC(31, 663, 0, 0) /* stfsx */
5291 case AFMOVSU:
5292 return OPVCC(31, 695, 0, 0) /* stfsux */
5293 case AFMOVSX:
5294 return OPVCC(31, 983, 0, 0) /* stfiwx */
5295
5296 case AMOVHZ, AMOVH:
5297 return OPVCC(31, 407, 0, 0) /* sthx */
5298 case AMOVHBR:
5299 return OPVCC(31, 918, 0, 0) /* sthbrx */
5300
5301 case AMOVHZU, AMOVHU:
5302 return OPVCC(31, 439, 0, 0) /* sthux */
5303
5304 case AMOVWZ, AMOVW:
5305 return OPVCC(31, 151, 0, 0) /* stwx */
5306
5307 case AMOVWZU, AMOVWU:
5308 return OPVCC(31, 183, 0, 0) /* stwux */
5309 case ASTSW:
5310 return OPVCC(31, 661, 0, 0) /* stswx */
5311 case AMOVWBR:
5312 return OPVCC(31, 662, 0, 0) /* stwbrx */
5313 case AMOVDBR:
5314 return OPVCC(31, 660, 0, 0) /* stdbrx */
5315 case ASTBCCC:
5316 return OPVCC(31, 694, 0, 1) /* stbcx. */
5317 case ASTHCCC:
5318 return OPVCC(31, 726, 0, 1) /* sthcx. */
5319 case ASTWCCC:
5320 return OPVCC(31, 150, 0, 1) /* stwcx. */
5321 case ASTDCCC:
5322 return OPVCC(31, 214, 0, 1) /* stwdx. */
5323 case AECOWX:
5324 return OPVCC(31, 438, 0, 0) /* ecowx */
5325 case AMOVD:
5326 return OPVCC(31, 149, 0, 0) /* stdx */
5327 case AMOVDU:
5328 return OPVCC(31, 181, 0, 0) /* stdux */
5329
5330 /* Vector (VMX/Altivec) instructions */
5331 case ASTVEBX:
5332 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */
5333 case ASTVEHX:
5334 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */
5335 case ASTVEWX:
5336 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */
5337 case ASTVX:
5338 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */
5339 case ASTVXL:
5340 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */
5341 /* End of vector instructions */
5342
5343 /* Vector scalar (VSX) instructions */
5344 case ASTXVX:
5345 return OPVXX1(31, 396, 0) /* stxvx - v3.0 */
5346 case ASTXVD2X:
5347 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */
5348 case ASTXVW4X:
5349 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */
5350 case ASTXVH8X:
5351 return OPVXX1(31, 940, 0) /* stxvh8x - v3.0 */
5352 case ASTXVB16X:
5353 return OPVXX1(31, 1004, 0) /* stxvb16x - v3.0 */
5354
5355 case ASTXSDX:
5356 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */
5357
5358 case ASTXSIWX:
5359 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */
5360
5361 /* End of vector scalar instructions */
5362
5363 }
5364
5365 c.ctxt.Diag("unknown storex opcode %v", a)
5366 return 0
5367 }
5368