atomic_arch.h raw

   1  #define a_ll a_ll
   2  static inline int a_ll(volatile int *p)
   3  {
   4  	int v;
   5  	__asm__ __volatile__ ("lwarx %0, 0, %2" : "=r"(v) : "m"(*p), "r"(p));
   6  	return v;
   7  }
   8  
   9  #define a_sc a_sc
  10  static inline int a_sc(volatile int *p, int v)
  11  {
  12  	int r;
  13  	__asm__ __volatile__ (
  14  		"stwcx. %2, 0, %3 ; mfcr %0"
  15  		: "=r"(r), "=m"(*p) : "r"(v), "r"(p) : "memory", "cc");
  16  	return r & 0x20000000; /* "bit 2" of "cr0" (backwards bit order) */
  17  }
  18  
  19  #define a_barrier a_barrier
  20  static inline void a_barrier()
  21  {
  22  	__asm__ __volatile__ ("sync" : : : "memory");
  23  }
  24  
  25  #define a_pre_llsc a_barrier
  26  
  27  #define a_post_llsc a_post_llsc
  28  static inline void a_post_llsc()
  29  {
  30  	__asm__ __volatile__ ("isync" : : : "memory");
  31  }
  32  
  33  #define a_clz_32 a_clz_32
  34  static inline int a_clz_32(uint32_t x)
  35  {
  36  	__asm__ ("cntlzw %0, %1" : "=r"(x) : "r"(x));
  37  	return x;
  38  }
  39