cpu_arm64.mx raw

   1  // Copyright 2017 The Go Authors. All rights reserved.
   2  // Use of this source code is governed by a BSD-style
   3  // license that can be found in the LICENSE file.
   4  
   5  package cpu
   6  
   7  // CacheLinePadSize is used to prevent false sharing of cache lines.
   8  // We choose 128 because Apple Silicon, a.k.a. M1, has 128-byte cache line size.
   9  // It doesn't cost much and is much more future-proof.
  10  const CacheLinePadSize = 128
  11  
  12  func doinit() {
  13  	options = []option{
  14  		{Name: "aes", Feature: &ARM64.HasAES},
  15  		{Name: "pmull", Feature: &ARM64.HasPMULL},
  16  		{Name: "sha1", Feature: &ARM64.HasSHA1},
  17  		{Name: "sha2", Feature: &ARM64.HasSHA2},
  18  		{Name: "sha512", Feature: &ARM64.HasSHA512},
  19  		{Name: "sha3", Feature: &ARM64.HasSHA3},
  20  		{Name: "crc32", Feature: &ARM64.HasCRC32},
  21  		{Name: "atomics", Feature: &ARM64.HasATOMICS},
  22  		{Name: "cpuid", Feature: &ARM64.HasCPUID},
  23  		{Name: "isNeoverse", Feature: &ARM64.IsNeoverse},
  24  	}
  25  
  26  	// arm64 uses different ways to detect CPU features at runtime depending on the operating system.
  27  	osInit()
  28  }
  29  
  30  func getisar0() uint64
  31  
  32  func getpfr0() uint64
  33  
  34  func getMIDR() uint64
  35  
  36  func extractBits(data uint64, start, end uint) uint {
  37  	return (uint)(data>>start) & ((1 << (end - start + 1)) - 1)
  38  }
  39  
  40  func parseARM64SystemRegisters(isar0, pfr0 uint64) {
  41  	// ID_AA64ISAR0_EL1
  42  	// https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0
  43  	switch extractBits(isar0, 4, 7) {
  44  	case 1:
  45  		ARM64.HasAES = true
  46  	case 2:
  47  		ARM64.HasAES = true
  48  		ARM64.HasPMULL = true
  49  	}
  50  
  51  	switch extractBits(isar0, 8, 11) {
  52  	case 1:
  53  		ARM64.HasSHA1 = true
  54  	}
  55  
  56  	switch extractBits(isar0, 12, 15) {
  57  	case 1:
  58  		ARM64.HasSHA2 = true
  59  	case 2:
  60  		ARM64.HasSHA2 = true
  61  		ARM64.HasSHA512 = true
  62  	}
  63  
  64  	switch extractBits(isar0, 16, 19) {
  65  	case 1:
  66  		ARM64.HasCRC32 = true
  67  	}
  68  
  69  	switch extractBits(isar0, 20, 23) {
  70  	case 2:
  71  		ARM64.HasATOMICS = true
  72  	}
  73  
  74  	switch extractBits(isar0, 32, 35) {
  75  	case 1:
  76  		ARM64.HasSHA3 = true
  77  	}
  78  
  79  	switch extractBits(pfr0, 48, 51) {
  80  	case 1:
  81  		ARM64.HasDIT = true
  82  	}
  83  }
  84